Lines Matching defs:Cond
157 /// setting TBB to the destination basic block and populating the Cond vector
162 SmallVectorImpl<MachineOperand> &Cond) {
171 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
172 Cond.push_back(I->getOperand(0));
180 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
181 Cond.push_back(I->getOperand(0));
182 Cond.push_back(I->getOperand(1));
194 SmallVectorImpl<MachineOperand> &Cond,
220 classifyCondBranch(LastInst, TBB, Cond);
256 Cond.push_back(MachineOperand::CreateImm(AArch64::Bcc));
257 Cond.push_back(SecondLastInst->getOperand(0));
261 classifyCondBranch(SecondLastInst, TBB, Cond);
282 SmallVectorImpl<MachineOperand> &Cond) const {
283 switch (Cond[0].getImm()) {
285 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(Cond[1].getImm());
287 Cond[1].setImm(CC);
291 Cond[0].setImm(AArch64::CBNZw);
294 Cond[0].setImm(AArch64::CBNZx);
297 Cond[0].setImm(AArch64::CBZw);
300 Cond[0].setImm(AArch64::CBZx);
303 Cond[0].setImm(AArch64::TBNZwii);
306 Cond[0].setImm(AArch64::TBNZxii);
309 Cond[0].setImm(AArch64::TBZwii);
312 Cond[0].setImm(AArch64::TBZxii);
323 const SmallVectorImpl<MachineOperand> &Cond,
325 if (FBB == 0 && Cond.empty()) {
329 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
330 for (int i = 1, e = Cond.size(); i != e; ++i)
331 MIB.addOperand(Cond[i]);
336 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
337 for (int i = 1, e = Cond.size(); i != e; ++i)
338 MIB.addOperand(Cond[i]);