Target/AArch64/AArch64ISelDAGToDAG.cpp

752   unsigned Vec0Idx = 3;
753   EVT VT = N->getOperand(Vec0Idx).getValueType();
780   SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Idx,
781                                N->op_begin() + Vec0Idx + NumVecs);
877   unsigned Vec0Idx = 3;
881       cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
882   EVT VT = N->getOperand(Vec0Idx).getValueType();
925   SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Idx,
926                                N->op_begin() + Vec0Idx + NumVecs);
1004   unsigned Vec0Idx = IsExt ? 2 : 1;
1005   assert(!N->getOperand(Vec0Idx + 0).getValueType().is64BitVector() &&
1013   SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Idx,
1014                                N->op_begin() + Vec0Idx + NumVecs);
1022   Ops.push_back(N->getOperand(Vec0Idx + NumVecs));