CodeGen/SelectionDAG/LegalizeVectorOps.cpp

401     EVT WideVT = TLI.getPointerTy();
403     assert(WideVT.isRound() &&
406     assert(WideVT.bitsGE(SrcEltVT) &&
409     unsigned WideBytes = WideVT.getStoreSize();
419         ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
425         EVT LoadVT = WideVT;
430         ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
448     SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, WideVT);
452     unsigned WideBits = WideVT.getSizeInBits();
458         ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
459         Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
460         Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
469                                   TLI.getShiftAmountTy(WideVT));
470           Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
471           Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
476         Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
488                                 TLI.getShiftAmountTy(WideVT));
489         Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
490         Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);