Lines Matching refs:Kill
221 IntegerReg, /*Kill=*/false);
920 IntReg, /*Kill=*/true,
927 ISD::BITCAST, IntResultReg, /*Kill=*/true);
1200 MaterialReg, /*Kill=*/true);
1224 .addReg(Op0, Op0IsKill * RegState::Kill);
1227 .addReg(Op0, Op0IsKill * RegState::Kill);
1244 .addReg(Op0, Op0IsKill * RegState::Kill)
1245 .addReg(Op1, Op1IsKill * RegState::Kill);
1248 .addReg(Op0, Op0IsKill * RegState::Kill)
1249 .addReg(Op1, Op1IsKill * RegState::Kill);
1266 .addReg(Op0, Op0IsKill * RegState::Kill)
1267 .addReg(Op1, Op1IsKill * RegState::Kill)
1268 .addReg(Op2, Op2IsKill * RegState::Kill);
1271 .addReg(Op0, Op0IsKill * RegState::Kill)
1272 .addReg(Op1, Op1IsKill * RegState::Kill)
1273 .addReg(Op2, Op2IsKill * RegState::Kill);
1289 .addReg(Op0, Op0IsKill * RegState::Kill)
1293 .addReg(Op0, Op0IsKill * RegState::Kill)
1310 .addReg(Op0, Op0IsKill * RegState::Kill)
1315 .addReg(Op0, Op0IsKill * RegState::Kill)
1333 .addReg(Op0, Op0IsKill * RegState::Kill)
1337 .addReg(Op0, Op0IsKill * RegState::Kill)
1355 .addReg(Op0, Op0IsKill * RegState::Kill)
1356 .addReg(Op1, Op1IsKill * RegState::Kill)
1360 .addReg(Op0, Op0IsKill * RegState::Kill)
1361 .addReg(Op1, Op1IsKill * RegState::Kill)
1379 .addReg(Op0, Op0IsKill * RegState::Kill)
1380 .addReg(Op1, Op1IsKill * RegState::Kill)
1384 .addReg(Op0, Op0IsKill * RegState::Kill)
1385 .addReg(Op1, Op1IsKill * RegState::Kill)