lib/CodeGen/ScheduleDAGInstrs.cpp

243 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
244   const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
274         SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
285 /// depend the physical register referenced at OperIdx.
286 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
288   const MachineOperand &MO = MI->getOperand(OperIdx);
313             SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
325     Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg()));
328     addPhysRegDataDeps(SU, OperIdx);
355     Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
361 /// from or write to the virtual register defined at OperIdx.
365 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
367   unsigned Reg = MI->getOperand(OperIdx).getReg();
390         SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
398 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
403 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
405   unsigned Reg = MI->getOperand(OperIdx).getReg();
435       dep.setLatency(SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx));