Lines Matching defs:MRI
68 MachineRegisterInfo *MRI;
328 MRI = &MF.getRegInfo();
331 PreRegAlloc = MRI->isSSA();
772 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
773 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
782 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
827 bool isKill = isOperandKill(MO, MRI);
856 else if (!isNew && isOperandKill(MO, MRI)) {
938 if (!MRI->isConstantPhysReg(Reg, *I.getParent()->getParent()))
955 assert(MRI->getVRegDef(Reg) &&
960 if (CurLoop->contains(MRI->getVRegDef(Reg)))
981 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
982 UE = MRI->use_end(); UI != UE; ++UI) {
1011 if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg))
1014 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
1015 E = MRI->use_nodbg_end(); I != E; ++I) {
1029 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i))
1122 } else if (isOperandKill(MO, MRI)) {
1200 } else if (isOperandKill(MO, MRI)) {
1266 unsigned Reg = MRI->createVirtualRegister(RC);
1320 if (TII->produceSameValue(MI, PrevMI, (PreRegAlloc ? MRI : 0)))
1358 OrigRCs.push_back(MRI->getRegClass(DupReg));
1360 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
1363 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
1372 MRI->replaceRegWith(Reg, DupReg);
1373 MRI->clearKillFlags(DupReg);
1445 MRI->clearKillFlags(MO.getReg());