config/ia64/ia64.c

699 /* Return 1 if the operands of a move are ok.  */
722 /* Return 1 if the operands are ok for a floating point load pair.  */
1314 ia64_split_tmode_move (rtx operands[])
1326   if (GET_CODE (operands[1]) == MEM
1327       && reg_overlap_mentioned_p (operands[0], operands[1]))
1329       rtx base = XEXP (operands[1], 0);
1333       if (REGNO (base) == REGNO (operands[0]))
1340   if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1341       && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1344   fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1345   fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1408 ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[])
1410   rtx op0 = operands[0];
1431       if ((GET_CODE (operands[1]) == SUBREG
1432 	   && GET_MODE (SUBREG_REG (operands[1])) == TImode)
1433 	  || (GET_CODE (operands[1]) == REG
1434 	      && GR_REGNO_P (REGNO (operands[1]))))
1436 	  rtx op1 = operands[1];
1447       if (GET_CODE (operands[1]) == CONST_DOUBLE)
1451 			  operand_subword (operands[1], WORDS_BIG_ENDIAN,
1454 			  operand_subword (operands[1], !WORDS_BIG_ENDIAN,
1460       if (register_operand (operands[1], mode))
1461 	operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
1463       gcc_assert (GET_CODE (operands[1]) == MEM);
1469       emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1470       emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1474   if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
1484       if (register_operand (operands[0], mode))
1486 	  rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
1488 	  operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode);
1495 	  gcc_assert (GET_CODE (operands[0]) == MEM);
1498 	  in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
1499 	  in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1501 	  emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1502 	  emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1509       operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
1513 	  rtx memt, memx, in = operands[1];
1528       if (!ia64_move_ok (operands[0], operands[1]))
1529 	operands[1] = force_reg (mode, operands[1]);
1718 ia64_expand_vecint_cmov (rtx operands[])
1720   enum machine_mode mode = GET_MODE (operands[0]);
1721   enum rtx_code code = GET_CODE (operands[3]);
1727 				       operands[4], operands[5]);
1729   ot = operands[1+negate];
1730   of = operands[2-negate];
1736 	  emit_move_insn (operands[0], ot);
1742       emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1747       emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1754       x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1759       x = gen_rtx_AND (mode, x, operands[2-negate]);
1763       emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1771 			   rtx operands[])
1786       x = gen_rtx_US_MINUS (mode, operands[1], operands[2]);
1789       emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2]));
1794   xops[0] = operands[0];
1795   xops[4] = xops[1] = operands[1];
1796   xops[5] = xops[2] = operands[2];
1815   xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
1824 ia64_expand_widen_sum (rtx operands[3], bool unsignedp)
1832   wmode = GET_MODE (operands[0]);
1833   mode = GET_MODE (operands[1]);
1860       neg = ia64_expand_vecint_compare (LT, mode, x, operands[1],
1869   emit_insn (unpack_l (gen_lowpart (mode, l), operands[1], x));
1870   emit_insn (unpack_h (gen_lowpart (mode, h), operands[1], x));
1871   emit_insn (plus (s, l, operands[2]));
1872   emit_insn (plus (operands[0], h, s));
1878 ia64_expand_dot_prod_v8qi (rtx operands[4], bool unsignedp)
1892       neg = ia64_expand_vecint_compare (LT, V8QImode, x1, operands[1],
1895       neg = ia64_expand_vecint_compare (LT, V8QImode, x2, operands[2],
1905   emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l1), operands[1], x1));
1906   emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l2), operands[2], x2));
1907   emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h1), operands[1], x1));
1908   emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h2), operands[2], x2));
1924   emit_insn (gen_addv2si3 (s3, s1, operands[3]));
1925   emit_insn (gen_addv2si3 (operands[0], s2, s3));
4468 /* ??? Do we need this?  It gets used only for 'a' operands.  We could perhaps
4989 	 registers as operands.  If the third operand is a constant, then it
5605       /* For all ASM_OPERANDS, we must traverse the vector of input operands.