binutils/opcodes/ppc-opc.c

1256 #define OP_MASK OP (0x3f)
1262 #define OPTO_MASK (OP_MASK | TO_MASK)
1327 #define DRA_MASK (OP_MASK | RA_MASK)
1373 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1688 { "tdi",     OP(2),	OP_MASK,	PPC64,		{ TO, RA, SI } },
1718 { "twi",     OP(3),	OP_MASK,	PPCCOM,		{ TO, RA, SI } },
1719 { "ti",      OP(3),	OP_MASK,	PWRCOM,		{ TO, RA, SI } },
2246 { "mulli",   OP(7),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2247 { "muli",    OP(7),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2249 { "subfic",  OP(8),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2250 { "sfi",     OP(8),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2252 { "dozi",    OP(9),	OP_MASK,	M601,		{ RT, RA, SI } },
2261 { "cmpli",   OP(10),	OP_MASK,	PPC,		{ BF, L, RA, UI } },
2262 { "cmpli",   OP(10),	OP_MASK,	PWRCOM,		{ BF, RA, UI } },
2266 { "cmpi",    OP(11),	OP_MASK,	PPC,		{ BF, L, RA, SI } },
2267 { "cmpi",    OP(11),	OP_MASK,	PWRCOM,		{ BF, RA, SI } },
2269 { "addic",   OP(12),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2270 { "ai",	     OP(12),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2271 { "subic",   OP(12),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
2273 { "addic.",  OP(13),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2274 { "ai.",     OP(13),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2275 { "subic.",  OP(13),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
2279 { "addi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA0, SI } },
2280 { "cal",     OP(14),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
2281 { "subi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA0, NSI } },
2282 { "la",	     OP(14),	OP_MASK,	PPCCOM,		{ RT, D, RA0 } },
2286 { "addis",   OP(15),	OP_MASK,	PPCCOM,		{ RT,RA0,SISIGNOPT } },
2287 { "cau",     OP(15),	OP_MASK,	PWRCOM,		{ RT,RA0,SISIGNOPT } },
2288 { "subis",   OP(15),	OP_MASK,	PPCCOM,		{ RT, RA0, NSI } },
3015 { "ori",     OP(24),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3016 { "oril",    OP(24),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3018 { "oris",    OP(25),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3019 { "oriu",    OP(25),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3021 { "xori",    OP(26),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3022 { "xoril",   OP(26),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3024 { "xoris",   OP(27),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3025 { "xoriu",   OP(27),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3027 { "andi.",   OP(28),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3028 { "andil.",  OP(28),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3030 { "andis.",  OP(29),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3031 { "andiu.",  OP(29),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
4286 { "lwz",     OP(32),	OP_MASK,	PPCCOM,		{ RT, D, RA0 } },
4287 { "l",	     OP(32),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
4289 { "lwzu",    OP(33),	OP_MASK,	PPCCOM,		{ RT, D, RAL } },
4290 { "lu",      OP(33),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
4292 { "lbz",     OP(34),	OP_MASK,	COM,		{ RT, D, RA0 } },
4294 { "lbzu",    OP(35),	OP_MASK,	COM,		{ RT, D, RAL } },
4296 { "stw",     OP(36),	OP_MASK,	PPCCOM,		{ RS, D, RA0 } },
4297 { "st",      OP(36),	OP_MASK,	PWRCOM,		{ RS, D, RA0 } },
4299 { "stwu",    OP(37),	OP_MASK,	PPCCOM,		{ RS, D, RAS } },
4300 { "stu",     OP(37),	OP_MASK,	PWRCOM,		{ RS, D, RA0 } },
4302 { "stb",     OP(38),	OP_MASK,	COM,		{ RS, D, RA0 } },
4304 { "stbu",    OP(39),	OP_MASK,	COM,		{ RS, D, RAS } },
4306 { "lhz",     OP(40),	OP_MASK,	COM,		{ RT, D, RA0 } },
4308 { "lhzu",    OP(41),	OP_MASK,	COM,		{ RT, D, RAL } },
4310 { "lha",     OP(42),	OP_MASK,	COM,		{ RT, D, RA0 } },
4312 { "lhau",    OP(43),	OP_MASK,	COM,		{ RT, D, RAL } },
4314 { "sth",     OP(44),	OP_MASK,	COM,		{ RS, D, RA0 } },
4316 { "sthu",    OP(45),	OP_MASK,	COM,		{ RS, D, RAS } },
4318 { "lmw",     OP(46),	OP_MASK,	PPCCOM,		{ RT, D, RAM } },
4319 { "lm",      OP(46),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
4321 { "stmw",    OP(47),	OP_MASK,	PPCCOM,		{ RS, D, RA0 } },
4322 { "stm",     OP(47),	OP_MASK,	PWRCOM,		{ RS, D, RA0 } },
4324 { "lfs",     OP(48),	OP_MASK,	COM,		{ FRT, D, RA0 } },
4326 { "lfsu",    OP(49),	OP_MASK,	COM,		{ FRT, D, RAS } },
4328 { "lfd",     OP(50),	OP_MASK,	COM,		{ FRT, D, RA0 } },
4330 { "lfdu",    OP(51),	OP_MASK,	COM,		{ FRT, D, RAS } },
4332 { "stfs",    OP(52),	OP_MASK,	COM,		{ FRS, D, RA0 } },
4334 { "stfsu",   OP(53),	OP_MASK,	COM,		{ FRS, D, RAS } },
4336 { "stfd",    OP(54),	OP_MASK,	COM,		{ FRS, D, RA0 } },
4338 { "stfdu",   OP(55),	OP_MASK,	COM,		{ FRS, D, RAS } },
4340 { "lq",      OP(56),	OP_MASK,	POWER4,		{ RTQ, DQ, RAQ } },
4342 { "lfq",     OP(56),	OP_MASK,	POWER2,		{ FRT, D, RA0 } },
4344 { "lfqu",    OP(57),	OP_MASK,	POWER2,		{ FRT, D, RA0 } },
4346 { "lfdp",    OP(57),	OP_MASK,	POWER6,		{ FRT, D, RA0 } },
4469 { "stfq",    OP(60),	OP_MASK,	POWER2,		{ FRS, D, RA } },
4471 { "stfqu",   OP(61),	OP_MASK,	POWER2,		{ FRS, D, RA } },
4473 { "stfdp",   OP(61),	OP_MASK,	POWER6,		{ FRT, D, RA0 } },