Lines Matching refs:Reg16
1445 { Reg16, "r16" },
2341 else if (i.types[op] & Reg16)
2851 i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX :
2878 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2998 (flag_code == CODE_32BIT ? Reg16 : Reg32))
3084 (i.op[op].regs + (i.types[op] & Reg16
3119 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3130 && (i.types[op] & Reg16) != 0
3173 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3183 else if (((i.types[op] & Reg16) != 0
3205 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3217 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
3600 else if (i.base_reg->reg_type & Reg16)
4077 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4946 ? Reg16
4974 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4975 != (Reg16 | BaseIndex)))
4977 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4978 != (Reg16 | BaseIndex))
5289 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
6817 && (i.base_reg->reg_type & Reg16)
6818 && (i.index_reg->reg_type & Reg16)
7392 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7557 if (reg->reg_type & Reg16)