Lines Matching defs:imm
329 signed int imm;
333 unsigned immisreg : 1; /* .imm field is a second register. */
3983 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4000 generic_bignum[0]. Make sure we put 32 bits in imm and
4003 inst.operands[i].imm = 0;
4005 inst.operands[i].imm |= generic_bignum[idx]
4116 is_quarter_float (unsigned imm)
4118 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4119 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4212 (LSL|LSR|ASL|ASR|ROR) #imm
4286 inst.operands[i].imm = reg;
4537 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4538 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4546 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4547 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4552 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4606 inst.operands[i].imm = reg;
4625 inst.operands[i].imm = exp.X_add_number << 8;
4709 if (parse_immediate (&p, &inst.operands[i].imm,
4745 inst.operands[i].imm |= reg;
4747 inst.operands[i].imm = reg;
5072 inst.operands[0].imm = reg;
5168 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5169 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5170 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5171 Case 10: VMOV.F32 <Sd>, #<imm>
5172 Case 11: VMOV.F64 <Dd>, #<imm> */
5214 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5215 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5410 OP_RR_EXi, /* ARM register or expression with imm prefix */
5492 inst.operands[i].imm = val; \
5769 inst.operands[i].imm = val;
6000 inst.operands[i].imm = val;
6183 inst.instruction |= inst.operands[i].imm << 8;
6253 inst.instruction |= inst.operands[i].imm;
6292 inst.instruction |= inst.operands[i].imm;
6327 inst.instruction |= inst.operands[i].imm;
6515 inst.instruction |= inst.operands[0].imm;
6578 && inst.operands[0].imm != 0xf,
6580 inst.instruction |= inst.operands[0].imm;
6589 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6594 inst.instruction |= inst.operands[1].imm << 7;
6608 msb = inst.operands[2].imm + inst.operands[3].imm;
6614 inst.instruction |= inst.operands[2].imm << 7;
6621 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6625 inst.instruction |= inst.operands[2].imm << 7;
6626 inst.instruction |= (inst.operands[3].imm - 1) << 16;
6639 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
6642 inst.instruction |= inst.operands[0].imm & 0xf;
6650 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
6751 inst.instruction |= inst.operands[1].imm << 20;
6755 inst.instruction |= inst.operands[5].imm << 5;
6777 inst.instruction |= inst.operands[1].imm << 21;
6785 inst.instruction |= inst.operands[5].imm << 5;
6805 inst.instruction |= inst.operands[1].imm << 4;
6814 inst.instruction |= inst.operands[0].imm << 6;
6818 inst.instruction |= inst.operands[1].imm;
6825 inst.instruction |= inst.operands[0].imm;
6840 int range = inst.operands[1].imm;
6909 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
6910 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7060 bfd_vma imm;
7071 imm = inst.reloc.exp.X_add_number;
7073 inst.instruction |= (imm & 0x00000fff);
7074 inst.instruction |= (imm & 0x0000f000) << 4;
7175 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
7179 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
7192 inst.instruction |= inst.operands[0].imm;
7246 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
7355 inst.instruction |= (inst.operands[1].imm - 1) << 16;
7368 inst.instruction |= inst.operands[1].imm << 16;
7381 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
7389 inst.instruction |= inst.operands[1].imm << 16;
7402 if (inst.operands[0].imm)
7498 inst.instruction |= inst.operands[1].imm;
7565 inst.instruction |= inst.operands[3].imm << 10;
7579 inst.instruction |= inst.operands[2].imm << 10;
7631 constraint (inst.operands[2].imm != 2,
7648 constraint (inst.operands[0].imm != 2,
7680 inst.instruction |= inst.operands[1].imm;
7697 count = inst.operands[1].imm << 1;
7788 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7789 inst.instruction |= (inst.operands[1].imm & 0x0f);
7796 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7797 inst.instruction |= (inst.operands[1].imm & 0x0f);
7803 unsigned immbits = srcsize - inst.operands[1].imm;
7851 switch (inst.operands[1].imm)
7871 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
7900 inst.instruction |= inst.operands[1].imm;
7908 inst.instruction |= inst.operands[2].imm;
7916 inst.instruction |= inst.operands[2].imm;
7933 inst.instruction |= inst.operands[3].imm << 20;
7942 inst.instruction |= inst.operands[3].imm << 21;
7997 inst.instruction |= inst.operands[1].imm;
8008 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
8009 inst.instruction |= (inst.operands[2].imm & 0x0f);
8030 if (inst.operands[2].imm == 0)
8039 inst.operands[2].imm = 16;
8047 inst.operands[2].imm = 32;
8066 inst.operands[2].imm &= 0x1f;
8067 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
8111 int imm = inst.operands[2].imm;
8119 imm = (imm & 0xf) | ((imm & 0x70) << 1);
8121 inst.instruction |= imm;
8229 inst.instruction |= inst.operands[i].imm;
8550 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
8806 && inst.operands[0].imm != 0xf,
8808 inst.instruction |= inst.operands[0].imm;
8817 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8822 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
8823 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
8837 msb = inst.operands[2].imm + inst.operands[3].imm;
8843 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8844 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8851 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8855 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8856 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8857 inst.instruction |= inst.operands[3].imm - 1;
8950 constraint (inst.operands[0].imm > 255,
8952 inst.instruction |= inst.operands[0].imm;
9007 inst.instruction |= inst.operands[0].imm;
9021 inst.instruction |= inst.operands[0].imm << 5;
9023 inst.instruction |= 0x100 | inst.operands[1].imm;
9028 && (inst.operands[0].imm & 4),
9034 inst.instruction |= inst.operands[0].imm;
9070 inst.instruction |= inst.operands[0].imm;
9095 unsigned int cond = inst.operands[0].imm;
9202 && !(inst.operands[1].imm & ~0xff))
9210 == !(inst.operands[1].imm & mask))))
9213 && (inst.operands[1].imm & mask)
9214 && (inst.operands[1].imm & (mask - 1)))
9220 inst.instruction |= inst.operands[1].imm;
9228 inst.instruction |= inst.operands[1].imm;
9238 encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm,
9245 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
9253 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
9254 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
9261 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
9264 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
9270 inst.instruction |= inst.operands[1].imm;
9335 if (Rn <= 7 && inst.operands[1].imm <= 7)
9387 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
9438 constraint (inst.operands[1].imm > 7, BAD_HIREG);
9458 inst.instruction |= inst.operands[1].imm << 6;
9569 if (!low_regs || inst.operands[1].imm > 7)
9597 inst.instruction |= inst.operands[1].imm << 3;
9606 inst.instruction |= inst.operands[1].imm;
9720 bfd_vma imm;
9738 imm = inst.reloc.exp.X_add_number;
9739 inst.instruction |= (imm & 0xf000) << 4;
9740 inst.instruction |= (imm & 0x0800) << 15;
9741 inst.instruction |= (imm & 0x0700) << 4;
9742 inst.instruction |= (imm & 0x00ff);
9821 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
9840 inst.instruction |= inst.operands[1].imm & 0xff;
9853 flags = inst.operands[0].imm;
9923 if (inst.size_req == 4 || inst.operands[0].imm > 15)
9926 inst.instruction |= inst.operands[0].imm;
9931 inst.instruction |= inst.operands[0].imm << 4;
10023 mask = inst.operands[0].imm;
10136 if (inst.operands[0].imm)
10262 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
10296 inst.instruction |= inst.operands[1].imm - 1;
10319 inst.instruction |= inst.operands[1].imm - 1;
10362 inst.instruction |= inst.operands[3].imm << 4;
10370 && (!inst.operands[2].present || inst.operands[2].imm == 0))
10382 inst.instruction |= inst.operands[2].imm << 4;
10386 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
10407 constraint (inst.operands[0].imm == 15,
10411 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
10418 inst.instruction |= inst.operands[1].imm;
10441 inst.instruction |= inst.operands[1].imm;
11638 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
11672 inst.operands[2].imm);
11764 neon_bits_same_in_bytes (unsigned imm)
11766 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
11767 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
11768 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
11769 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
11775 neon_squash_bits (unsigned imm)
11777 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
11778 | ((imm & 0x01000000) >> 21);
11784 neon_qfloat_bits (unsigned imm)
11786 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
11976 immbits = inst.operands[1].imm;
12402 int imm = inst.operands[2].imm;
12403 constraint (imm < 0 || (unsigned)imm >= et.size,
12405 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
12414 int imm = inst.operands[2].imm;
12415 constraint (imm < 1 || (unsigned)imm > et.size,
12417 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
12426 int imm = inst.operands[2].imm;
12427 constraint (imm < 0 || (unsigned)imm >= et.size,
12434 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
12469 int imm = inst.operands[2].imm;
12476 if (imm == 0)
12484 constraint (imm < 1 || (unsigned)imm > et.size,
12486 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
12496 int imm = inst.operands[2].imm;
12503 if (imm == 0)
12511 constraint (imm < 1 || (unsigned)imm > et.size,
12516 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
12533 int imm = inst.operands[2].imm;
12540 if (imm == 0)
12548 constraint (imm < 1 || (unsigned)imm > et.size,
12550 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
12559 unsigned imm = inst.operands[2].imm;
12561 if (imm == et.size)
12579 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
12744 if (inst.operands[2].present && inst.operands[2].imm == 0)
12746 unsigned immbits = 32 - inst.operands[2].imm;
12809 immlo = inst.operands[1].imm;
12983 unsigned imm = (inst.operands[3].imm * et.size) / 8;
12984 constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range"));
12992 inst.instruction |= imm << 8;
13069 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13070 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13083 10. VMOV.F32 <Sd>, #imm
13084 11. VMOV.F64 <Dd>, #imm
13270 if (is_quarter_float (inst.operands[1].imm))
13272 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
13294 inst.operands[2].imm = 2;
13304 inst.operands[0].imm = 2;
13319 int imm = inst.operands[2].imm;
13321 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13322 if (imm == 0)
13329 constraint (imm < 1 || (unsigned)imm > et.size,
13332 et.size - imm);
13440 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
13446 listlenbits = inst.operands[1].imm - 1;
13463 unsigned offsetbits = inst.operands[1].imm * 2;
13474 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
13537 switch (inst.operands[1].imm >> 8)
13541 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13546 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13564 idx = ((inst.operands[0].imm >> 4) & 7)
13622 int align = inst.operands[1].imm >> 8;
13629 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
13631 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
13633 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
13694 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13697 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
13715 assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
13716 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13720 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
13730 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13734 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
13736 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13744 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
13746 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13753 int align = inst.operands[1].imm >> 8;
13758 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
13760 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13781 switch (NEON_LANE (inst.operands[0].imm))
13805 int postreg = inst.operands[1].imm & 0xf;