Lines Matching refs:val
55 uint32_t val;
57 val = rt305x_sysctl_get(r); printf(" " #r "=%#08x\n", val)
59 val = rt305x_sysctl_get(SYSCTL_CHIPID0_3);
61 (val >> 0 ) & 0xff,
62 (val >> 8 ) & 0xff,
63 (val >> 16) & 0xff,
64 (val >> 24) & 0xff);
65 val = rt305x_sysctl_get(SYSCTL_CHIPID4_7);
67 (val >> 0 ) & 0xff,
68 (val >> 8 ) & 0xff,
69 (val >> 16) & 0xff,
70 (val >> 24) & 0xff);
73 if ( val & SYSCTL_SYSCFG_INIC_EE_SDRAM)
75 if ( val & SYSCTL_SYSCFG_INIC_8MB_SDRAM)
78 ((val & SYSCTL_SYSCFG_GE0_MODE_MASK) >>
80 if ( val & SYSCTL_SYSCFG_BOOT_ADDR_1F00)
82 if ( val & SYSCTL_SYSCFG_BYPASS_PLL)
84 if ( val & SYSCTL_SYSCFG_BIG_ENDIAN)
86 if ( val & SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ)
89 ((val & SYSCTL_SYSCFG_BOOT_FROM_MASK) >>
92 ((val & SYSCTL_SYSCFG_TEST_CODE_MASK) >>
95 ((val & SYSCTL_SYSCFG_SRAM_CS_MODE_MASK) >>
98 (val & SYSCTL_SYSCFG_SDRAM_CLK_DRV)?12:8);
101 printf("\tSDRAM_CLK_SKEW %uns\n", (val >> 30) & 0x03);
104 if ( val & SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2)
106 if ( val & SYSCTL_CLKCFG1_OTG_CLK_EN)
108 if ( val & SYSCTL_CLKCFG1_I2S_CLK_EN)
111 (val & SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT)?
114 ((val & SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK) >>
116 if ( val & SYSCTL_CLKCFG1_PCM_CLK_EN)
120 (val & SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT)?
123 ((val & SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK) >>
217 rt305x_sysctl_set(uint32_t reg, uint32_t val)
220 bus_write_4(sc->mem_res, reg, val);