Lines Matching refs:temp
287 uint32_t temp;
291 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
292 if (temp & XHCI_CRCR_LO_CRR) {
294 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
303 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
306 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
313 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
314 if (temp & XHCI_CRCR_LO_CRR) {
351 uint32_t temp;
372 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
374 DPRINTF("HCS0 = 0x%08x\n", temp);
376 if (XHCI_HCS0_CSZ(temp)) {
389 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
391 if (!temp)
395 if (temp) {
407 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
409 i = XHCI_HCS1_N_PORTS(temp);
418 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
432 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
434 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
444 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
446 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
447 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
449 temp = XREAD4(sc, oper, XHCI_USBSTS);
452 XWRITE4(sc, oper, XHCI_USBSTS, temp);
482 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
484 DPRINTF("HCS2=0x%08x\n", temp);
486 temp = XHCI_HCS2_ERST_MAX(temp);
487 temp = 1U << temp;
488 if (temp > XHCI_MAX_RSEG)
489 temp = XHCI_MAX_RSEG;
491 sc->sc_erst_max = temp;
494 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
496 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
531 temp = XREAD4(sc, runt, XHCI_IMAN(0));
532 temp |= XHCI_IMAN_INTR_ENA;
533 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
554 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
555 if (!temp)
558 if (temp) {
578 uint32_t temp;
593 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
594 if (temp)
598 if (!temp) {
862 uint32_t temp;
873 temp = le32toh(trb->dwTrb2);
875 remainder = XHCI_TRB_2_REM_GET(temp);
876 status = XHCI_TRB_2_ERROR_GET(temp);
877 stream_id = XHCI_TRB_2_STREAM_GET(temp);
879 temp = le32toh(trb->dwTrb3);
880 epno = XHCI_TRB_3_EP_GET(temp);
881 index = XHCI_TRB_3_SLOT_GET(temp);
945 temp = le32toh(td->td_trb[i].dwTrb2);
946 remainder += XHCI_TRB_2_BYTES_GET(temp);
1041 uint32_t temp;
1063 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1065 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1070 event = XHCI_TRB_3_TYPE_GET(temp);
1130 uint32_t temp;
1162 temp = trb->dwTrb3;
1165 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1167 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1169 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1171 phwr->hwr_commands[i].dwTrb3 = temp;
1185 temp = htole32(XHCI_TRB_3_TC_BIT |
1189 temp = htole32(XHCI_TRB_3_TC_BIT |
1193 phwr->hwr_commands[i].dwTrb3 = temp;
1229 temp = le32toh(trb->dwTrb3);
1236 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1237 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1251 temp = le32toh(sc->sc_cmd_result[0]);
1252 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1269 uint32_t temp;
1275 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1277 trb.dwTrb3 = htole32(temp);
1287 uint32_t temp;
1300 temp = le32toh(trb.dwTrb3);
1302 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1312 uint32_t temp;
1318 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1321 trb.dwTrb3 = htole32(temp);
1331 uint32_t temp;
1337 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1341 temp |= XHCI_TRB_3_BSR_BIT;
1343 trb.dwTrb3 = htole32(temp);
1357 uint32_t temp;
1424 temp = le32toh(sc->sc_cmd_result[0]);
1426 XHCI_TRB_2_ERROR_GET(temp) ==
1444 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1445 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1473 uint32_t temp;
1479 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1483 temp |= XHCI_TRB_3_DCEP_BIT;
1485 trb.dwTrb3 = htole32(temp);
1495 uint32_t temp;
1501 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1503 trb.dwTrb3 = htole32(temp);
1513 uint32_t temp;
1519 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1524 temp |= XHCI_TRB_3_PRSV_BIT;
1526 trb.dwTrb3 = htole32(temp);
1536 uint32_t temp;
1542 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1543 trb.dwTrb2 = htole32(temp);
1545 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1548 trb.dwTrb3 = htole32(temp);
1558 uint32_t temp;
1564 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1569 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1571 trb.dwTrb3 = htole32(temp);
1580 uint32_t temp;
1586 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1589 trb.dwTrb3 = htole32(temp);
1601 uint32_t temp;
1613 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1616 if (temp & XHCI_IMAN_INTR_PEND)
1617 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1674 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1692 shortpkt_old = temp->shortpkt;
1693 len_old = temp->len;
1699 td = temp->td;
1700 td_next = td_first = temp->td_next;
1704 if (temp->len == 0) {
1706 if (temp->shortpkt)
1711 temp->shortpkt = 1;
1716 average = temp->average;
1718 if (temp->len < average) {
1719 if (temp->len % temp->max_packet_size) {
1720 temp->shortpkt = 1;
1722 average = temp->len;
1740 temp->len -= average;
1752 temp->len -= average;
1758 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1766 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1804 usbd_get_page(temp->pc, temp->offset +
1819 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1820 temp->max_packet_size;
1838 switch (temp->trb_type) {
1841 XHCI_TRB_3_TBC_SET(temp->tbc) |
1842 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1845 } else if (temp->do_isoc_sync != 0) {
1846 temp->do_isoc_sync = 0;
1849 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1855 if (temp->direction == UE_DIR_IN)
1861 if (temp->direction == UE_DIR_IN)
1867 if (temp->direction == UE_DIR_IN)
1873 if (temp->direction == UE_DIR_IN)
1936 if (temp->last_frame) {
1944 temp->shortpkt = shortpkt_old;
1945 temp->len = len_old;
1953 if (temp->step_td != 0) {
1967 temp->td = td;
1968 temp->td_next = td_next;
1974 struct xhci_std_temp temp;
1980 temp.do_isoc_sync = 0;
1981 temp.step_td = 0;
1982 temp.tbc = 0;
1983 temp.tlbpc = 0;
1984 temp.average = xfer->max_hc_frame_size;
1985 temp.max_packet_size = xfer->max_packet_size;
1986 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1987 temp.pc = NULL;
1988 temp.last_frame = 0;
1989 temp.offset = 0;
1990 temp.multishort = xfer->flags_int.isochronous_xfr ||
2000 temp.td = NULL;
2001 temp.td_next = td;
2024 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2031 temp.isoc_delta = 8; /* 1ms */
2032 x += temp.isoc_delta - 1;
2033 x &= ~(temp.isoc_delta - 1);
2037 temp.isoc_delta = 1U << shift;
2038 x += temp.isoc_delta - 1;
2039 x &= ~(temp.isoc_delta - 1);
2059 temp.do_isoc_sync = 1;
2069 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2073 temp.isoc_frame = xfer->endpoint->isoc_next;
2074 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2084 temp.len = xfer->frlengths[0];
2085 temp.pc = xfer->frbuffers + 0;
2086 temp.shortpkt = temp.len ? 1 : 0;
2087 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2088 temp.direction = 0;
2094 temp.last_frame = 1;
2097 xhci_setup_generic_chain_sub(&temp);
2101 temp.isoc_delta = 0;
2102 temp.isoc_frame = 0;
2103 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
2107 temp.isoc_delta = 0;
2108 temp.isoc_frame = 0;
2109 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2114 temp.pc = xfer->frbuffers + x;
2116 temp.direction = UE_GET_DIR(xfer->endpointno);
2123 temp.len = xfer->frlengths[x];
2124 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2125 x != 0 && temp.multishort == 0);
2133 temp.last_frame = 1;
2135 temp.last_frame = 1;
2138 if (temp.len == 0) {
2142 temp.shortpkt = 0;
2144 temp.tbc = 0;
2145 temp.tlbpc = mult - 1;
2156 temp.shortpkt = 1;
2160 if (temp.len > xfer->max_frame_size)
2161 temp.len = xfer->max_frame_size;
2164 tdpc = (temp.len + xfer->max_packet_size - 1) /
2167 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2168 temp.tlbpc = (tdpc % mult);
2170 if (temp.tlbpc == 0)
2171 temp.tlbpc = mult - 1;
2173 temp.tlbpc--;
2178 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2181 xhci_setup_generic_chain_sub(&temp);
2184 temp.offset += xfer->frlengths[x - 1];
2185 temp.isoc_frame += temp.isoc_delta;
2188 temp.pc = xfer->frbuffers + x;
2201 temp.step_td = (xfer->nframes != 0);
2202 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2203 temp.len = 0;
2204 temp.pc = NULL;
2205 temp.shortpkt = 0;
2206 temp.last_frame = 1;
2207 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2209 xhci_setup_generic_chain_sub(&temp);
2212 td = temp.td;
2244 uint32_t temp;
2285 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2286 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2287 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2288 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2304 uint32_t temp;
2339 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2346 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2367 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2370 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2376 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2387 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2389 temp =
2396 temp |= XHCI_EPCTX_1_CERR_SET(3);
2401 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2404 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2407 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2410 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2416 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2418 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2424 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2429 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2432 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2436 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2459 uint64_t temp;
2465 temp = pepext->physaddr +
2471 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2497 uint32_t temp;
2545 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2551 temp |= XHCI_SCTX_0_SPEED_SET(2);
2556 temp |= XHCI_SCTX_0_MTT_SET(1);
2560 temp |= XHCI_SCTX_0_SPEED_SET(3);
2564 temp |= XHCI_SCTX_0_MTT_SET(1);
2568 temp |= XHCI_SCTX_0_SPEED_SET(1);
2573 temp |= XHCI_SCTX_0_MTT_SET(1);
2577 temp |= XHCI_SCTX_0_SPEED_SET(4);
2586 temp |= XHCI_SCTX_0_HUB_SET(1);
2588 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2590 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2593 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2603 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2614 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2616 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2619 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2630 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2632 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2640 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2646 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2649 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
3263 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3314 sc->sc_hub_desc.temp,
3315 sizeof(sc->sc_hub_desc.temp),
3326 sc->sc_hub_desc.temp[0] = 0;
3471 memset(sc->sc_hub_desc.temp, 0, 16);
4005 uint8_t temp;
4019 err = xhci_cmd_enable_slot(sc, &temp);
4026 if (temp > sc->sc_noslot) {
4031 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4032 DPRINTF("slot %u already allocated.\n", temp);
4039 udev->controller_slot_id = temp;
4043 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4047 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;