usb/controller/dwc_otg.c

365 	uint32_t temp;
368 	temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK;
369 	if (temp >= 10000)
370 		temp /= 1000;
372 		temp /= 125;
375 	if (temp >= 54)
376 		temp = 60;	/* MHz */
377 	else if (temp >= 39)
378 		temp = 48;	/* MHz */
380 		temp = 30;	/* MHz */
383 		temp *= 125;
385 		temp *= 1000;
387 	DPRINTF("HFIR=0x%08x\n", temp);
389 	DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp);
423 	uint32_t temp;
431 		temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
432 		temp &= ~DCTL_SFTDISCON;
433 		DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
440 	uint32_t temp;
447 		temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
448 		temp |= DCTL_SFTDISCON;
449 		DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
519 		uint32_t temp;
522 		temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
523 		temp |= DCTL_RMTWKUPSIG;
524 		DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
529 		temp &= ~DCTL_RMTWKUPSIG;
530 		DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
560 	uint32_t temp;
564 	temp = DWC_OTG_READ_4(sc, DOTG_DCFG);
565 	temp &= ~DCFG_DEVADDR_SET(0x7F);
566 	temp |= DCFG_DEVADDR_SET(addr);
567 	DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp);
936 	uint32_t temp;
1006 	temp = sc->sc_in_ctl[0];
1010 	    temp | DIEPCTL_EPENA);
1012 	    temp | DIEPCTL_SNAK);
1026 	temp = sc->sc_out_ctl[0];
1028 	temp |= DOEPCTL_EPENA |
1032 	DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp);
1041 		    temp | DOEPCTL_STALL);
1043 		temp = sc->sc_in_ctl[0];
1047 		    temp | DIEPCTL_STALL);
1484 	uint32_t temp;
1568 	temp = sc->sc_out_ctl[td->ep_no];
1570 	temp |= DOEPCTL_EPENA | DOEPCTL_CNAK;
1572 	DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp);
1972 	uint32_t temp;
1982 	temp = sc->sc_last_rx_status;
1984 	if ((td->ep_no == 0) && (temp != 0) &&
1985 	    (GRXSTSRD_CHNUM_GET(temp) == 0)) {
1987 		if ((temp & GRXSTSRD_PKTSTS_MASK) !=
2008 		temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2011 		cpkt = DXEPTSIZ_GET_NPKT(temp);
2066 	temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2068 	if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2072 		    DXEPTSIZ_GET_NPKT(temp),
2073 		    temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no)));
2130 	temp = sc->sc_in_ctl[td->ep_no];
2133 	DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp |
2156 	uint32_t temp;
2161 	temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2164 	if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2174 	temp = sc->sc_last_rx_status;
2176 	if ((td->ep_no == 0) && (temp != 0) &&
2177 	    (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2179 		if ((temp & GRXSTSRD_PKTSTS_MASK) ==
2366 	uint16_t temp;
2370 	temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK;
2372 	if (sc->sc_last_frame_num == temp)
2375 	sc->sc_last_frame_num = temp;
2388 	if ((temp & 7) == 0) {
2421 			td->tt_start_slot = temp + slot;
2445 			td->tt_start_slot = temp;
2471 			td->tt_start_slot = temp;
2492 			td->tt_start_slot = temp;
2498 	if ((temp & 7) < 6) {
2513 			td->tt_start_slot = temp;
2544 	if ((temp & 7) == 0) {
2547 		    (int)temp, (int)sc->sc_needsof);
2572 	uint32_t temp;
2579 		temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
2580 		if (temp != 0) {
2581 			DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp);
2582 			temp &= ~HCINT_SOFTWARE_ONLY;
2583 			sc->sc_chan_state[x].hcint |= temp;
2589 		temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2590 		if (temp & GINTSTS_RXFLVL) {
2600 			temp = sc->sc_last_rx_status &
2604 			if (temp != GRXSTSRD_STP_DATA &&
2605 			    temp != GRXSTSRD_OUT_DATA) {
2610 			temp = GRXSTSRD_BCNT_GET(
2616 			if (temp != 0) {
2617 				DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no);
2620 				    sc->sc_rx_bounce_buffer, (temp + 3) / 4);
2736 		uint32_t temp;
2740 			temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x));
2741 			if (temp & DIEPMSK_XFERCOMPLMSK) {
2798 		uint32_t temp;
2818 		temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
2819 		if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI)
2926 		uint32_t temp;
2928 		temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
2930 		DPRINTFN(5, "GOTGCTL=0x%08x\n", temp);
2933 		    (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
2953 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp)
2958 	td = temp->td_next;
2959 	temp->td = td;
2962 	temp->td_next = td->obj_next;
2965 	td->func = temp->func;
2966 	td->pc = temp->pc;
2967 	td->offset = temp->offset;
2968 	td->remainder = temp->len;
2973 	td->did_stall = temp->did_stall;
2974 	td->short_pkt = temp->short_pkt;
2975 	td->alt_next = temp->setup_alt_next;
2989 	struct dwc_otg_std_temp temp;
2999 	temp.max_frame_size = xfer->max_frame_size;
3005 	/* setup temp */
3007 	temp.pc = NULL;
3008 	temp.td = NULL;
3009 	temp.td_next = xfer->td_start[0];
3010 	temp.offset = 0;
3011 	temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
3013 	temp.did_stall = !xfer->flags_int.control_stall;
3023 				temp.func = &dwc_otg_host_setup_tx;
3025 				temp.func = &dwc_otg_setup_rx;
3027 			temp.len = xfer->frlengths[0];
3028 			temp.pc = xfer->frbuffers + 0;
3029 			temp.short_pkt = temp.len ? 1 : 0;
3035 					temp.setup_alt_next = 0;
3038 			dwc_otg_setup_standard_chain_sub(&temp);
3048 				temp.func = &dwc_otg_host_data_rx;
3051 				temp.func = &dwc_otg_data_tx;
3056 				temp.func = &dwc_otg_host_data_tx;
3059 				temp.func = &dwc_otg_data_rx;
3065 		temp.pc = xfer->frbuffers + x;
3073 		temp.len = xfer->frlengths[x];
3080 					temp.setup_alt_next = 0;
3083 				temp.setup_alt_next = 0;
3086 		if (temp.len == 0) {
3090 			temp.short_pkt = 0;
3096 			temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
3099 		dwc_otg_setup_standard_chain_sub(&temp);
3102 			temp.offset += temp.len;
3105 			temp.pc = xfer->frbuffers + x;
3112 		temp.pc = xfer->frbuffers + 0;
3113 		temp.len = 0;
3114 		temp.short_pkt = 0;
3115 		temp.setup_alt_next = 0;
3120 			temp.func = &dwc_otg_data_tx_sync;
3121 			dwc_otg_setup_standard_chain_sub(&temp);
3133 					temp.func = &dwc_otg_host_data_tx;
3136 					temp.func = &dwc_otg_data_rx;
3141 					temp.func = &dwc_otg_host_data_rx;
3144 					temp.func = &dwc_otg_data_tx;
3149 			dwc_otg_setup_standard_chain_sub(&temp);
3152 			td = temp.td;
3157 				temp.func = &dwc_otg_data_tx_sync;
3158 				dwc_otg_setup_standard_chain_sub(&temp);
3165 			temp.pc = xfer->frbuffers + 0;
3166 			temp.len = 0;
3167 			temp.short_pkt = 0;
3168 			temp.setup_alt_next = 0;
3171 			temp.func = &dwc_otg_data_tx_sync;
3172 			dwc_otg_setup_standard_chain_sub(&temp);
3177 	td = temp.td;
3534 	uint32_t temp;
3557 		temp = sc->sc_in_ctl[ep_no & UE_ADDR];
3560 		temp = sc->sc_out_ctl[ep_no & UE_ADDR];
3564 	DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3565 	DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL);
3590 	uint32_t temp;
3608 		temp = DIEPCTL_EPTYPE_SET(
3612 		temp = DIEPCTL_EPTYPE_SET(
3616 		temp = DIEPCTL_EPTYPE_SET(
3621 	temp |= DIEPCTL_MPS_SET(mps);
3622 	temp |= DIEPCTL_TXFNUM_SET(ep_no);
3625 		sc->sc_in_ctl[ep_no] = temp;
3627 		sc->sc_out_ctl[ep_no] = temp;
3629 	DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3630 	DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID);
3631 	DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK);
3721 	uint32_t temp;
3737 	temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID);
3738 	DPRINTF("Version = 0x%08x\n", temp);
3755 		temp = GUSBCFG_FORCEDEVMODE;
3758 		temp = GUSBCFG_FORCEHOSTMODE;
3761 		temp = 0;
3769 		    GUSBCFG_TRD_TIM_SET(5) | temp);
3773 		temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3775 		    temp & ~GLPMCFG_HSIC_CONN);
3777 		    temp | GLPMCFG_HSIC_CONN);
3781 		    GUSBCFG_TRD_TIM_SET(5) | temp);
3784 		temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3786 		    temp & ~GLPMCFG_HSIC_CONN);
3809 	temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3);
3811 	sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp);
3813 	temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
3815 	sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp);
3820 	sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp);
3825 	temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4);
3827 	sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp);
3846 		temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
3847 		if (temp & GHWCFG2_MPI) {
3868 		temp = DWC_OTG_READ_4(sc, DOTG_HCFG);
3869 		temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK);
3870 		temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT);
3871 		DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp);
3883 	temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
3885 	DPRINTFN(5, "GOTCTL=0x%08x\n", temp);
3888 	    (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
4020 	uint32_t temp;
4029 		temp = DWC_OTG_READ_4(sc, DOTG_HFNUM);
4032 		framenum = (temp & HFNUM_FRNUM_MASK);
4034 		temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
4037 		framenum = DSTS_SOFFN_GET(temp);
4058 	temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK;
4060 	if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) {
4075 	temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK;
4081 		usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes;