drm2/radeon/radeon_cp.c

901 	u32 temp;
909 		temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
920 		temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
926 		temp = dev_priv->gart_info.bus_addr & 0xfffff000;
927 		temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
928 		IGP_WRITE_MCIND(RS480_GART_BASE, temp);
930 		temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
937 		temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
940 		radeon_write_agp_location(dev_priv, temp);
942 		temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
947 			temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
948 			if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
957 			temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
958 			if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
972 	u32 temp;
1016 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1017 		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1019 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1020 		IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1023 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1025 		temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1026 		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1027 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1029 		temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1030 		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1031 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1033 		temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1034 		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1035 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1039 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1040 		temp &= ~RS600_ENABLE_PAGE_TABLES;
1041 		IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);