Lines Matching defs:lvds
1526 struct radeon_encoder_atom_dig *lvds = NULL;
1533 lvds =
1537 if (!lvds)
1540 lvds->native_mode.clock =
1542 lvds->native_mode.hdisplay =
1544 lvds->native_mode.vdisplay =
1546 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1548 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1550 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1552 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1554 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1556 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1558 lvds->panel_pwr_delay =
1560 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1564 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1566 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1568 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1570 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1572 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1574 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1575 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1578 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1580 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1582 encoder->native_mode = lvds->native_mode;
1585 lvds->linkb = true;
1587 lvds->linkb = false;
1638 lvds->native_mode.width_mm = panel_res_record->usHSize;
1639 lvds->native_mode.height_mm = panel_res_record->usVSize;
1652 return lvds;