drm2/radeon/r200.c

158 	u32 idx_value;
162 	idx_value = radeon_get_ib_value(p, idx);
190 		track->zb.offset = idx_value;
192 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
203 		track->cb[0].offset = idx_value;
205 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
227 			tmp = idx_value & ~(0x7 << 2);
231 			ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
274 		track->textures[i].cube_info[face - 1].offset = idx_value;
275 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
280 		track->maxy = ((idx_value >> 16) & 0x7FF);
299 			tmp = idx_value & ~(0x7 << 16);
303 			ib[idx] = idx_value;
305 		track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
309 		track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
313 		switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
331 				  ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
334 		if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
339 		track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
344 		switch (idx_value & 0xf) {
369 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
373 			uint32_t temp = idx_value >> 4;
380 		track->vap_vf_cntl = idx_value;
384 		track->max_indx = idx_value & 0x00FFFFFFUL;
387 		track->vtx_size = r200_get_vtx_size_0(idx_value);
390 		track->vtx_size += r200_get_vtx_size_1(idx_value);
399 		track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
400 		track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
410 		track->textures[i].pitch = idx_value + 32;
420 		track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
422 		tmp = (idx_value >> 23) & 0x7;
425 		tmp = (idx_value >> 27) & 0x7;
445 		track->textures[i].txdepth = idx_value & 0x7;
446 		tmp = (idx_value >> 16) & 0x3;
476 		if (idx_value & R200_TXFORMAT_NON_POWER2) {
480 			track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
481 			track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
483 		if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)
485 		switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
522 		track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
523 		track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
532 		tmp = idx_value;