Lines Matching refs:gb_addr_config
434 u32 gb_addr_config = 0;
467 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
518 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
547 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
549 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
551 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
553 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
555 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
557 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
561 /* setup tiling info dword. gb_addr_config is not adequate since it does
603 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
605 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
623 WREG32(GB_ADDR_CONFIG, gb_addr_config);
624 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
625 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
626 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
627 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
629 tmp = gb_addr_config & NUM_PIPES_MASK;