Lines Matching defs:idx_value
1994 u32 idx_value;
1999 idx_value = radeon_get_ib_value(p, idx);
2032 (idx_value & 0xfffffff0) +
2078 idx_value +
2105 idx_value +
2222 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
2235 if (idx_value & 0x10) {
2435 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2451 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
2471 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
2574 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
2584 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
2594 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
2608 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
2623 if (idx_value & 0x1) {
2642 if (((idx_value >> 1) & 0x3) == 2) {
2695 if (idx_value & 0x1) {
2719 if (idx_value & 0x2) {
2890 u32 idx, idx_value;
2947 idx_value = radeon_get_ib_value(p, idx + 2);
2952 if (idx_value & (1U << 31)) {
2995 if (idx_value & (1U << 31)) {
3012 if (idx_value & (1U << 31)) {
3051 if (idx_value & (1U << 31)) {
3096 if (idx_value & (1U << 31)) {
3140 if (idx_value & (1U << 31)) {
3441 u32 idx_value = ib[idx];
3490 if (idx_value & 0x100) {
3497 if (idx_value & 0x2) {
3504 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
3536 start_reg = idx_value << 2;