Lines Matching refs:temp
2389 u32 temp;
2397 temp = I915_READ(0x4600c);
2398 temp &= 0xffff0000;
2399 I915_WRITE(0x4600c, temp | 0x8124);
2401 temp = I915_READ(0x46010);
2402 I915_WRITE(0x46010, temp | 1);
2404 temp = I915_READ(0x46034);
2405 I915_WRITE(0x46034, temp | (1 << 24));
2421 u32 reg, temp;
2425 temp = I915_READ(reg);
2427 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2428 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2433 I915_WRITE(reg, temp);
2436 temp = I915_READ(reg);
2438 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2439 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2441 temp &= ~FDI_LINK_TRAIN_NONE;
2442 temp |= FDI_LINK_TRAIN_NONE;
2444 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2476 u32 reg, temp, tries;
2485 temp = I915_READ(reg);
2486 temp &= ~FDI_RX_SYMBOL_LOCK;
2487 temp &= ~FDI_RX_BIT_LOCK;
2488 I915_WRITE(reg, temp);
2494 temp = I915_READ(reg);
2495 temp &= ~(7 << 19);
2496 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2497 temp &= ~FDI_LINK_TRAIN_NONE;
2498 temp |= FDI_LINK_TRAIN_PATTERN_1;
2499 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2502 temp = I915_READ(reg);
2503 temp &= ~FDI_LINK_TRAIN_NONE;
2504 temp |= FDI_LINK_TRAIN_PATTERN_1;
2505 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2519 temp = I915_READ(reg);
2520 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522 if ((temp & FDI_RX_BIT_LOCK)) {
2524 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2533 temp = I915_READ(reg);
2534 temp &= ~FDI_LINK_TRAIN_NONE;
2535 temp |= FDI_LINK_TRAIN_PATTERN_2;
2536 I915_WRITE(reg, temp);
2539 temp = I915_READ(reg);
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_2;
2542 I915_WRITE(reg, temp);
2549 temp = I915_READ(reg);
2550 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2552 if (temp & FDI_RX_SYMBOL_LOCK) {
2553 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2579 u32 reg, temp, i;
2584 temp = I915_READ(reg);
2585 temp &= ~FDI_RX_SYMBOL_LOCK;
2586 temp &= ~FDI_RX_BIT_LOCK;
2587 I915_WRITE(reg, temp);
2594 temp = I915_READ(reg);
2595 temp &= ~(7 << 19);
2596 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2597 temp &= ~FDI_LINK_TRAIN_NONE;
2598 temp |= FDI_LINK_TRAIN_PATTERN_1;
2599 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2601 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2602 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2605 temp = I915_READ(reg);
2607 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2608 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2610 temp &= ~FDI_LINK_TRAIN_NONE;
2611 temp |= FDI_LINK_TRAIN_PATTERN_1;
2613 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2623 temp = I915_READ(reg);
2624 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2625 temp |= snb_b_fdi_train_param[i];
2626 I915_WRITE(reg, temp);
2632 temp = I915_READ(reg);
2633 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2635 if (temp & FDI_RX_BIT_LOCK) {
2636 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_NONE;
2648 temp |= FDI_LINK_TRAIN_PATTERN_2;
2650 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2654 I915_WRITE(reg, temp);
2657 temp = I915_READ(reg);
2659 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2660 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2662 temp &= ~FDI_LINK_TRAIN_NONE;
2663 temp |= FDI_LINK_TRAIN_PATTERN_2;
2665 I915_WRITE(reg, temp);
2672 temp = I915_READ(reg);
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= snb_b_fdi_train_param[i];
2675 I915_WRITE(reg, temp);
2681 temp = I915_READ(reg);
2682 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2684 if (temp & FDI_RX_SYMBOL_LOCK) {
2685 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2703 u32 reg, temp, i;
2708 temp = I915_READ(reg);
2709 temp &= ~FDI_RX_SYMBOL_LOCK;
2710 temp &= ~FDI_RX_BIT_LOCK;
2711 I915_WRITE(reg, temp);
2718 temp = I915_READ(reg);
2719 temp &= ~(7 << 19);
2720 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2721 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2722 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2723 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2725 temp |= FDI_COMPOSITE_SYNC;
2726 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2729 temp = I915_READ(reg);
2730 temp &= ~FDI_LINK_TRAIN_AUTO;
2731 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2732 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2733 temp |= FDI_COMPOSITE_SYNC;
2734 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2741 temp = I915_READ(reg);
2742 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743 temp |= snb_b_fdi_train_param[i];
2744 I915_WRITE(reg, temp);
2750 temp = I915_READ(reg);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2753 if (temp & FDI_RX_BIT_LOCK ||
2755 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2765 temp = I915_READ(reg);
2766 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2767 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2768 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2769 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2770 I915_WRITE(reg, temp);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2775 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2776 I915_WRITE(reg, temp);
2783 temp = I915_READ(reg);
2784 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2785 temp |= snb_b_fdi_train_param[i];
2786 I915_WRITE(reg, temp);
2792 temp = I915_READ(reg);
2793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2795 if (temp & FDI_RX_SYMBOL_LOCK) {
2796 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2813 u32 reg, temp;
2821 temp = I915_READ(reg);
2822 temp &= ~((0x7 << 19) | (0x7 << 16));
2823 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2824 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2825 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2831 temp = I915_READ(reg);
2832 I915_WRITE(reg, temp | FDI_PCDCLK);
2839 temp = I915_READ(reg);
2840 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2841 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2866 u32 reg, temp;
2870 temp = I915_READ(reg);
2871 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2875 temp = I915_READ(reg);
2876 temp &= ~(0x7 << 16);
2877 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2878 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2895 temp = I915_READ(reg);
2896 temp &= ~FDI_LINK_TRAIN_NONE;
2897 temp |= FDI_LINK_TRAIN_PATTERN_1;
2898 I915_WRITE(reg, temp);
2901 temp = I915_READ(reg);
2903 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2904 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2910 temp &= ~(0x07 << 16);
2911 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2912 I915_WRITE(reg, temp);
2995 u32 reg, temp, transc_sel;
3007 temp = I915_READ(PCH_DPLL_SEL);
3009 temp &= ~(TRANSA_DPLLB_SEL);
3010 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3012 temp &= ~(TRANSB_DPLLB_SEL);
3013 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3015 temp &= ~(TRANSC_DPLLB_SEL);
3016 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
3018 I915_WRITE(PCH_DPLL_SEL, temp);
3040 temp = I915_READ(reg);
3041 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3044 temp |= (TRANS_DP_OUTPUT_ENABLE |
3046 temp |= bpc << 9; /* same format but at 11:9 */
3049 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3051 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3055 temp |= TRANS_DP_PORT_SEL_B;
3058 temp |= TRANS_DP_PORT_SEL_C;
3061 temp |= TRANS_DP_PORT_SEL_D;
3065 temp |= TRANS_DP_PORT_SEL_B;
3069 I915_WRITE(reg, temp);
3079 u32 temp;
3081 temp = I915_READ(dslreg);
3083 if (_intel_wait_for(dev, I915_READ(dslreg) != temp, 5, 1, "915cp1")) {
3088 if (_intel_wait_for(dev, I915_READ(dslreg) != temp, 5, 1,
3101 u32 temp;
3111 temp = I915_READ(PCH_LVDS);
3112 if ((temp & LVDS_PORT_EN) == 0)
3113 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3157 u32 reg, temp;
3191 temp = I915_READ(reg);
3192 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3193 temp |= TRANS_DP_PORT_SEL_NONE;
3194 I915_WRITE(reg, temp);
3197 temp = I915_READ(PCH_DPLL_SEL);
3200 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3203 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3207 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3212 I915_WRITE(PCH_DPLL_SEL, temp);
3221 temp = I915_READ(reg);
3222 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3226 temp = I915_READ(reg);
3227 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3233 temp = I915_READ(reg);
3234 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
5210 u32 temp;
5398 temp = I915_READ(LVDS);
5399 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5401 temp |= LVDS_PIPEB_SELECT;
5403 temp &= ~LVDS_PIPEB_SELECT;
5406 temp |= dev_priv->lvds_border_bits;
5411 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5413 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5422 temp |= LVDS_ENABLE_DITHER;
5424 temp &= ~LVDS_ENABLE_DITHER;
5430 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5435 flags[!(temp & LVDS_HSYNC_POLARITY)],
5436 flags[!(temp & LVDS_VSYNC_POLARITY)],
5439 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5440 temp |= lvds_sync;
5442 I915_WRITE(LVDS, temp);
5456 temp = 0;
5458 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5459 if (temp > 1)
5460 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5462 temp = 0;
5464 I915_WRITE(DPLL_MD(pipe), temp);
5556 u32 temp;
5599 temp = I915_READ(PCH_DREF_CONTROL);
5601 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5604 temp |= DREF_NONSPREAD_CK505_ENABLE;
5606 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5609 temp &= ~DREF_SSC_SOURCE_MASK;
5610 temp |= DREF_SSC_SOURCE_ENABLE;
5615 temp |= DREF_SSC1_ENABLE;
5617 temp &= ~DREF_SSC1_ENABLE;
5620 I915_WRITE(PCH_DREF_CONTROL, temp);
5624 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5630 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5633 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5635 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5637 I915_WRITE(PCH_DREF_CONTROL, temp);
5643 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5646 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5648 I915_WRITE(PCH_DREF_CONTROL, temp);
5653 temp &= ~DREF_SSC_SOURCE_MASK;
5654 temp |= DREF_SSC_SOURCE_DISABLE;
5657 temp &= ~ DREF_SSC1_ENABLE;
5659 I915_WRITE(PCH_DREF_CONTROL, temp);
5721 u32 temp;
5838 temp = I915_READ(PIPECONF(pipe));
5839 temp &= ~PIPE_BPC_MASK;
5843 temp |= PIPE_6BPC;
5846 temp |= PIPE_8BPC;
5849 temp |= PIPE_10BPC;
5852 temp |= PIPE_12BPC;
5857 temp |= PIPE_8BPC;
5863 I915_WRITE(PIPECONF(pipe), temp);
5986 temp = I915_READ(PCH_LVDS);
5987 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5989 temp &= ~PORT_TRANS_SEL_MASK;
5990 temp |= PORT_TRANS_SEL_CPT(pipe);
5993 temp |= LVDS_PIPEB_SELECT;
5995 temp &= ~LVDS_PIPEB_SELECT;
5999 temp |= dev_priv->lvds_border_bits;
6004 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
6006 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
6016 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
6021 flags[!(temp & LVDS_HSYNC_POLARITY)],
6022 flags[!(temp & LVDS_VSYNC_POLARITY)],
6025 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
6026 temp |= lvds_sync;
6028 I915_WRITE(PCH_LVDS, temp);
8128 /* Enable temp reporting */