ath_hal/ar5212/ar5212_attach.c

21 #include "ah.h"
32 static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
34 static void ar5212DisablePCIE(struct ath_hal *ah);
181 ar5212GetRadioRev(struct ath_hal *ah)
187 	OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16);
189 		OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
190 	val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
196 ar5212AniSetup(struct ath_hal *ah)
216 	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) {
220 		ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE);
222 		ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
225 	AH5212(ah)->ah_aniControl = ar5212AniControl;
238 	struct ath_hal *ah;
240 	ah = &ahp->ah_priv.h;
243 	ah->ah_sc = sc;
244 	ah->ah_st = st;
245 	ah->ah_sh = sh;
247 	ah->ah_devid = devid;			/* NB: for alq */
248 	AH_PRIVATE(ah)->ah_devid = devid;
249 	AH_PRIVATE(ah)->ah_subvendorid = 0;	/* XXX */
251 	AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
252 	AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX;	/* no scaling */
322 #define	AH_EEPROM_PROTECT(ah) \
323 	(AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)
325 	struct ath_hal *ah;
343 	ah = &ahp->ah_priv.h;
345 	if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
346 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
352 	val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
353 	AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
354 	AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
355 	AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah);
357 	if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) {
358 		HALDEBUG(ah, HAL_DEBUG_ANY,
360 		    __func__, AH_PRIVATE(ah)->ah_macVersion,
361 		    AH_PRIVATE(ah)->ah_macRev);
370 	if (!ar5212ChipReset(ah, AH_NULL)) {	/* reset chip */
371 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
376 	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
378 	if (AH_PRIVATE(ah)->ah_ispcie) {
380 		ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE);
383 	if (!ar5212ChipTest(ah)) {
384 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
391 	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE)
392 		OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN);
398 	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
401 	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
403 	rf = ath_hal_rfprobe(ah, &ecode);
408 	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
418 		if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
427 			if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
428 			    AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN &&
429 			    AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) {
430 				AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN;
433 			if (IS_2413(ah)) {		/* Griffin */
434 				AH_PRIVATE(ah)->ah_analog5GhzRev =
438 			if (IS_5413(ah)) {		/* Eagle */
439 				AH_PRIVATE(ah)->ah_analog5GhzRev =
443 			if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */
444 				AH_PRIVATE(ah)->ah_analog5GhzRev =
450 		HALDEBUG(ah, HAL_DEBUG_ANY,
453 		    __func__, AH_PRIVATE(ah)->ah_analog5GhzRev);
458 	if (IS_RAD5112_REV1(ah)) {
459 		HALDEBUG(ah, HAL_DEBUG_ANY,
462 		    AH_PRIVATE(ah)->ah_analog5GhzRev);
467 	val = OS_REG_READ(ah, AR_PCICFG);
470 		if (!AH_PRIVATE(ah)->ah_ispcie) {
471 			HALDEBUG(ah, HAL_DEBUG_ANY,
477 		/* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */
480 			HALDEBUG(ah, HAL_DEBUG_ANY,
486 		HALDEBUG(ah, HAL_DEBUG_ANY,
492 	ecode = ath_hal_legacyEepromAttach(ah);
496 	ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON);
501 	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) &&
502 	    (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) {
507 		OS_REG_WRITE(ah, AR_PHY(0), 0x00004007);
509 		AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah);
512 		OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
514 		if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) {
515 			HALDEBUG(ah, HAL_DEBUG_ANY,
518 			    AH_PRIVATE(ah)->ah_analog2GhzRev);
524 	ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);
526 		HALDEBUG(ah, HAL_DEBUG_ANY,
531 	AH_PRIVATE(ah)->ah_currentRD = eeval;
537 	if (!ar5212FillCapabilityInfo(ah)) {
538 		HALDEBUG(ah, HAL_DEBUG_ANY,
544 	if (!rf->attach(ah, &ecode)) {
545 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
553 	AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust;
556 	ar5212InitializeGainValues(ah);
558 	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
560 		HALDEBUG(ah, HAL_DEBUG_ANY,
565 	ar5212AniSetup(ah);
567 	ar5212InitNfCalHistBuffer(ah);
571 	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
573 	return ah;
585 ar5212Detach(struct ath_hal *ah)
587 	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
589 	HALASSERT(ah != AH_NULL);
590 	HALASSERT(ah->ah_magic == AR5212_MAGIC);
592 	ar5212AniDetach(ah);
593 	ar5212RfDetach(ah);
594 	ar5212Disable(ah);
595 	ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
597 	ath_hal_eepromDetach(ah);
598 	ath_hal_free(ah);
602 ar5212ChipTest(struct ath_hal *ah)
615 		regHold[i] = OS_REG_READ(ah, addr);
618 			OS_REG_WRITE(ah, addr, wrData);
619 			rdData = OS_REG_READ(ah, addr);
621 				HALDEBUG(ah, HAL_DEBUG_ANY,
629 			OS_REG_WRITE(ah, addr, wrData);
630 			rdData = OS_REG_READ(ah, addr);
632 				HALDEBUG(ah, HAL_DEBUG_ANY,
638 		OS_REG_WRITE(ah, regAddr[i], regHold[i]);
648 ar5212GetChannelEdges(struct ath_hal *ah,
657 	    (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) ||
658 	     ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) {
676 ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
678 	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
679 	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
682 	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
683 	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
684 	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
687 	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
688 	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
689 	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
690 	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
693 	OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
697 ar5212DisablePCIE(struct ath_hal *ah)
708 ar5212FillCapabilityInfo(struct ath_hal *ah)
711 #define	IS_GRIFFIN_LITE(ah) \
712     (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \
713      AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE)
714 #define	IS_COBRA(ah) \
715     (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA)
716 #define IS_2112(ah) \
717 	((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR)
719 	struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
724 	if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) {
725 		HALDEBUG(ah, HAL_DEBUG_ANY,
729 	if (IS_2112(ah))
730 		ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE);
731 	if (capField == 0 && IS_GRIFFIN_LITE(ah)) {
735 		ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
736 		ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
737 		ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
738 		ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
739 		HALDEBUG(ah, HAL_DEBUG_ATTACH,
752 		HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n",
756 	if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 ||
757 	    AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) {
758 		HALDEBUG(ah, HAL_DEBUG_ATTACH,
761 		ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE);
762 		ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
763 		ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
764 		ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
765 		ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
770 	if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
772 		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
775 	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
777 	if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
780 		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
786 	if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) ||  IS_2417(ah))
809 	if (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR) {
819 		(ath_hal_eepromGetFlag(ah, AR_EEP_AES) &&
820 		 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) ||
821 		  ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) &&
822 		   (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU))));
826 	pCap->halMicAesCcmSupport  = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
831 	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN)
838 	if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) {
840 			ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) &&
842 		pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST);
844 			ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) &&
862 	if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
867 	if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
881 	if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
882 	    ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
890 	    (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);
893 	if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
894 	     AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) ||
895 	    AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) {
910 	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN)