Lines Matching defs:ah
19 #include "ah.h"
40 ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level)
42 struct ath_hal_9300 *ahp = AH9300(ah);
46 if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD &&
55 omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0);
57 txcfg = OS_REG_READ(ah, AR_TXCFG);
71 OS_REG_WRITE(ah,
76 ar9300_set_interrupts(ah, omask, 0);
78 AH9300(ah)->ah_tx_trig_level = new_level;
87 ar9300_get_tx_trig_level(struct ath_hal *ah)
89 return (AH9300(ah)->ah_tx_trig_level);
97 ar9300_set_tx_queue_props(struct ath_hal *ah, int q, const HAL_TXQ_INFO *q_info)
99 struct ath_hal_9300 *ahp = AH9300(ah);
100 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
103 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
106 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], q_info);
113 ar9300_get_tx_queue_props(struct ath_hal *ah, int q, HAL_TXQ_INFO *q_info)
115 struct ath_hal_9300 *ahp = AH9300(ah);
116 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
120 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
123 return ath_hal_getTxQProps(ah, q_info, &ahp->ah_txq[q]);
137 ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type,
140 struct ath_hal_9300 *ahp = AH9300(ah);
142 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
175 HALDEBUG(ah, HAL_DEBUG_QUEUE,
181 HALDEBUG(ah, HAL_DEBUG_QUEUE,
186 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: queue %u\n", __func__, q);
190 HALDEBUG(ah, HAL_DEBUG_QUEUE,
212 (void) ar9300_set_tx_queue_props(ah, q, q_info);
222 set_tx_q_interrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
224 struct ath_hal_9300 *ahp = AH9300(ah);
226 HALDEBUG(ah, HAL_DEBUG_INTERRUPT,
234 OS_REG_WRITE(ah, AR_IMR_S0,
236 OS_REG_WRITE(ah, AR_IMR_S1,
239 OS_REG_RMW_FIELD(ah,
241 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2);
248 ar9300_release_tx_queue(struct ath_hal *ah, u_int q)
250 struct ath_hal_9300 *ahp = AH9300(ah);
251 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
255 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
261 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q);
265 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: release queue %u\n", __func__, q);
272 set_tx_q_interrupts(ah, qi);
283 ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
285 struct ath_hal_9300 *ahp = AH9300(ah);
286 // struct ath_hal_private *ap = AH_PRIVATE(ah);
287 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
288 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
293 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
299 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q);
303 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: reset queue %u\n", __func__, q);
322 if (q > 3 || (!AH9300(ah)->ah_fccaifs))
326 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(cw_min, AR_D_LCL_IFS_CWMIN)
332 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),
338 OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
341 if (AR_SREV_WASP(ah) && (AH_PRIVATE((ah))->ah_macRev <= AR_SREV_REVISION_WASP_12)) {
344 OS_REG_WRITE(ah, AR_DMISC(q),
347 OS_REG_WRITE(ah, AR_DMISC(q),
353 OS_REG_WRITE(ah,
358 OS_REG_WRITE(ah, AR_QMISC(q),
359 OS_REG_READ(ah, AR_QMISC(q)) |
366 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
371 OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
377 OS_REG_WRITE(ah, AR_QMISC(q), OS_REG_READ(ah, AR_QMISC(q)) |
382 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) |
387 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) |
393 OS_REG_WRITE(ah, AR_QMISC(q),
394 OS_REG_READ(ah, AR_QMISC(q))
399 OS_REG_WRITE(ah, AR_DMISC(q),
400 OS_REG_READ(ah, AR_DMISC(q))
406 if (AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS) {
407 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
419 OS_REG_WRITE(ah, AR_QMISC(q),
420 OS_REG_READ(ah, AR_QMISC(q))
426 - (ah->ah_config.ah_sw_beacon_response_time
427 - ah->ah_config.ah_dma_beacon_response_time)
428 - ah->ah_config.ah_additional_swba_backoff;
429 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN);
431 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q))
444 OS_REG_WRITE(ah, AR_QMISC(q),
445 OS_REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
448 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q))
464 OS_REG_WRITE(ah, AR_DMISC(q),
465 OS_REG_READ(ah, AR_DMISC(q)) |
472 OS_REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
504 set_tx_q_interrupts(ah, qi);
513 ar9300_get_tx_dp(struct ath_hal *ah, u_int q)
515 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
516 return OS_REG_READ(ah, AR_QTXDP(q));
523 ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp)
525 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
526 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
529 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
538 ar9300_start_tx_dma(struct ath_hal *ah, u_int q)
548 ar9300_num_tx_pending(struct ath_hal *ah, u_int q)
552 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
554 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
561 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) {
566 if (npend && (AH9300(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
567 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
568 HALDEBUG(ah, HAL_DEBUG_QUEUE, "RTSD on CAB queue\n");
570 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
575 (AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE));
584 ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout)
590 return ar9300_abort_tx_dma(ah);
597 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
599 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
605 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
608 if (ar9300_num_tx_pending(ah, q) == 0) {
616 HALDEBUG(ah, HAL_DEBUG_QUEUE,
618 HALDEBUG(ah, HAL_DEBUG_QUEUE,
621 OS_REG_READ(ah, AR_QSTS(q)),
622 OS_REG_READ(ah, AR_Q_TXE),
623 OS_REG_READ(ah, AR_Q_TXD),
624 OS_REG_READ(ah, AR_QCBRCFG(q)));
625 HALDEBUG(ah, HAL_DEBUG_QUEUE,
628 OS_REG_READ(ah, AR_QMISC(q)),
629 OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
630 OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
635 if (ar9300_num_tx_pending(ah, q)) {
638 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n",
639 __func__, ar9300_num_tx_pending(ah, q), q);
644 tsf_low = OS_REG_READ(ah, AR_TSF_L32);
645 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
646 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
647 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10);
648 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
650 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) {
654 HALDEBUG(ah, HAL_DEBUG_QUEUE,
662 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
666 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
670 while (ar9300_num_tx_pending(ah, q)) {
672 HALDEBUG(ah, HAL_DEBUG_TX,
681 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
684 OS_REG_WRITE(ah, AR_Q_TXD, 0);
696 ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout)
702 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
704 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
710 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
713 if (ar9300_num_tx_pending(ah, q) == 0) {
721 HALDEBUG(ah, HAL_DEBUG_QUEUE,
723 HALDEBUG(ah, HAL_DEBUG_QUEUE,
726 OS_REG_READ(ah, AR_QSTS(q)),
727 OS_REG_READ(ah, AR_Q_TXE),
728 OS_REG_READ(ah, AR_Q_TXD),
729 OS_REG_READ(ah, AR_QCBRCFG(q)));
730 HALDEBUG(ah, HAL_DEBUG_QUEUE,
733 OS_REG_READ(ah, AR_QMISC(q)),
734 OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
735 OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
740 if (ar9300_num_tx_pending(ah, q)) {
743 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n",
744 __func__, ar9300_num_tx_pending(ah, q), q);
749 tsf_low = OS_REG_READ(ah, AR_TSF_L32);
750 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
751 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
752 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10);
753 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
755 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) {
759 HALDEBUG(ah, HAL_DEBUG_QUEUE,
767 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
771 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
775 while (ar9300_num_tx_pending(ah, q)) {
777 HALDEBUG(ah, HAL_DEBUG_TX,
786 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
789 OS_REG_WRITE(ah, AR_Q_TXD, 0);
802 ar9300_abort_tx_dma(struct ath_hal *ah)
809 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
814 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
815 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
817 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
821 if (OS_REG_READ(ah, AR_Q_TXE) == 0) {
827 HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n",
836 if (!ar9300_num_tx_pending(ah, q)) {
842 HALDEBUG(ah, HAL_DEBUG_TX,
852 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
853 OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
855 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
860 OS_REG_WRITE(ah, AR_Q_TXD, 0);
869 ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs)
874 struct ath_hal_9300 *ahp = AH9300(ah);
881 ar9300_reset_tx_status_ring(struct ath_hal *ah)
883 struct ath_hal_9300 *ahp = AH9300(ah);
889 HALDEBUG(ah, HAL_DEBUG_QUEUE,
893 OS_REG_WRITE(ah, AR_Q_STATUS_RING_START, ahp->ts_paddr_start);
894 OS_REG_WRITE(ah, AR_Q_STATUS_RING_END, ahp->ts_paddr_end);
898 ar9300_setup_tx_status_ring(struct ath_hal *ah, void *ts_start,
901 struct ath_hal_9300 *ahp = AH9300(ah);
908 ar9300_reset_tx_status_ring(ah);