Lines Matching defs:opcode
357 EmulateInstructionARM::EmulatePUSH (const uint32_t opcode, const ARMEncoding encoding)
388 if (ConditionPassed(opcode, &conditional))
398 registers = Bits32(opcode, 7, 0);
400 if (Bit32(opcode, 8))
408 registers = Bits32(opcode, 15, 0) & ~0xa000;
414 Rt = Bits32(opcode, 15, 12);
421 registers = Bits32(opcode, 15, 0);
427 Rt = Bits32(opcode, 15, 12);
487 EmulateInstructionARM::EmulatePOP (const uint32_t opcode, const ARMEncoding encoding)
511 if (ConditionPassed(opcode, &conditional))
521 registers = Bits32(opcode, 7, 0);
523 if (Bit32(opcode, 8))
531 registers = Bits32(opcode, 15, 0) & ~0x2000;
533 if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14)))
540 Rt = Bits32(opcode, 15, 12);
549 registers = Bits32(opcode, 15, 0);
555 if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7)
559 Rt = Bits32(opcode, 15, 12);
619 EmulateInstructionARM::EmulateADDRdSPImm (const uint32_t opcode, const ARMEncoding encoding)
641 if (ConditionPassed(opcode))
651 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32)
654 Rd = Bits32(opcode, 15, 12);
655 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
678 EmulateInstructionARM::EmulateMOVRdSP (const uint32_t opcode, const ARMEncoding encoding)
700 if (ConditionPassed(opcode))
735 EmulateInstructionARM::EmulateMOVLowHigh (const uint32_t opcode, const ARMEncoding encoding)
737 return EmulateMOVRdRm (opcode, encoding);
743 EmulateInstructionARM::EmulateMOVRdRm (const uint32_t opcode, const ARMEncoding encoding)
765 if (ConditionPassed(opcode))
772 Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
773 Rm = Bits32(opcode, 6, 3);
779 Rd = Bits32(opcode, 2, 0);
780 Rm = Bits32(opcode, 5, 3);
786 Rd = Bits32(opcode, 11, 8);
787 Rm = Bits32(opcode, 3, 0);
788 setflags = BitIsSet(opcode, 20);
797 Rd = Bits32(opcode, 15, 12);
798 Rm = Bits32(opcode, 3, 0);
799 setflags = BitIsSet(opcode, 20);
803 return EmulateSUBSPcLrEtc (opcode, encoding);
829 EmulateInstructionARM::EmulateMOVRdImm (const uint32_t opcode, const ARMEncoding encoding)
849 if (ConditionPassed(opcode))
859 Rd = Bits32(opcode, 10, 8);
861 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
867 Rd = Bits32(opcode, 11, 8);
868 setflags = BitIsSet(opcode, 20);
869 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
878 Rd = Bits32 (opcode, 11, 8);
880 uint32_t imm4 = Bits32 (opcode, 19, 16);
881 uint32_t imm3 = Bits32 (opcode, 14, 12);
882 uint32_t i = Bit32 (opcode, 26);
883 uint32_t imm8 = Bits32 (opcode, 7, 0);
894 Rd = Bits32 (opcode, 15, 12);
895 setflags = BitIsSet (opcode, 20);
896 imm32 = ARMExpandImm_C (opcode, APSR_C, carry);
900 return EmulateSUBSPcLrEtc (opcode, encoding);
907 Rd = Bits32 (opcode, 15, 12);
909 uint32_t imm4 = Bits32 (opcode, 19, 16);
910 uint32_t imm12 = Bits32 (opcode, 11, 0);
942 EmulateInstructionARM::EmulateMUL (const uint32_t opcode, const ARMEncoding encoding)
960 if (ConditionPassed(opcode))
972 d = Bits32 (opcode, 2, 0);
973 n = Bits32 (opcode, 5, 3);
974 m = Bits32 (opcode, 2, 0);
985 d = Bits32 (opcode, 11, 8);
986 n = Bits32 (opcode, 19, 16);
987 m = Bits32 (opcode, 3, 0);
998 d = Bits32 (opcode, 19, 16);
999 n = Bits32 (opcode, 3, 0);
1000 m = Bits32 (opcode, 11, 8);
1001 setflags = BitIsSet (opcode, 20);
1069 EmulateInstructionARM::EmulateMVNImm (const uint32_t opcode, const ARMEncoding encoding)
1089 if (ConditionPassed(opcode))
1097 Rd = Bits32(opcode, 11, 8);
1098 setflags = BitIsSet(opcode, 20);
1099 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
1102 Rd = Bits32(opcode, 15, 12);
1103 setflags = BitIsSet(opcode, 20);
1104 imm32 = ARMExpandImm_C(opcode, APSR_C, carry);
1108 return EmulateSUBSPcLrEtc (opcode, encoding);
1129 EmulateInstructionARM::EmulateMVNReg (const uint32_t opcode, const ARMEncoding encoding)
1150 if (ConditionPassed(opcode))
1160 Rd = Bits32(opcode, 2, 0);
1161 Rm = Bits32(opcode, 5, 3);
1169 Rd = Bits32(opcode, 11, 8);
1170 Rm = Bits32(opcode, 3, 0);
1171 setflags = BitIsSet(opcode, 20);
1172 shift_n = DecodeImmShiftThumb(opcode, shift_t);
1178 Rd = Bits32(opcode, 15, 12);
1179 Rm = Bits32(opcode, 3, 0);
1180 setflags = BitIsSet(opcode, 20);
1181 shift_n = DecodeImmShiftARM(opcode, shift_t);
1210 EmulateInstructionARM::EmulateLDRRtPCRelative (const uint32_t opcode, const ARMEncoding encoding)
1232 if (ConditionPassed(opcode))
1254 Rt = Bits32(opcode, 10, 8);
1255 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32);
1259 Rt = Bits32(opcode, 15, 12);
1260 imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32);
1261 add = BitIsSet(opcode, 23);
1306 EmulateInstructionARM::EmulateADDSPImm (const uint32_t opcode, const ARMEncoding encoding)
1328 if (ConditionPassed(opcode))
1340 d = Bits32 (opcode, 10, 8);
1341 imm32 = (Bits32 (opcode, 7, 0) << 2);
1348 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
1390 EmulateInstructionARM::EmulateADDSPRm (const uint32_t opcode, const ARMEncoding encoding)
1413 if (ConditionPassed(opcode))
1421 Rm = Bits32(opcode, 6, 3);
1452 EmulateInstructionARM::EmulateBLXImmediate (const uint32_t opcode, const ARMEncoding encoding)
1474 if (ConditionPassed(opcode))
1488 uint32_t S = Bit32(opcode, 26);
1489 uint32_t imm10 = Bits32(opcode, 25, 16);
1490 uint32_t J1 = Bit32(opcode, 13);
1491 uint32_t J2 = Bit32(opcode, 11);
1492 uint32_t imm11 = Bits32(opcode, 10, 0);
1506 uint32_t S = Bit32(opcode, 26);
1507 uint32_t imm10H = Bits32(opcode, 25, 16);
1508 uint32_t J1 = Bit32(opcode, 13);
1509 uint32_t J2 = Bit32(opcode, 11);
1510 uint32_t imm10L = Bits32(opcode, 10, 1);
1523 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
1529 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | Bits32(opcode, 24, 24) << 1);
1548 EmulateInstructionARM::EmulateBLXRm (const uint32_t opcode, const ARMEncoding encoding)
1568 if (ConditionPassed(opcode))
1580 Rm = Bits32(opcode, 6, 3);
1589 Rm = Bits32(opcode, 3, 0);
1613 EmulateInstructionARM::EmulateBXRm (const uint32_t opcode, const ARMEncoding encoding)
1624 if (ConditionPassed(opcode))
1631 Rm = Bits32(opcode, 6, 3);
1636 Rm = Bits32(opcode, 3, 0);
1661 EmulateInstructionARM::EmulateBXJRm (const uint32_t opcode, const ARMEncoding encoding)
1678 if (ConditionPassed(opcode))
1685 Rm = Bits32(opcode, 19, 16);
1692 Rm = Bits32(opcode, 3, 0);
1716 EmulateInstructionARM::EmulateSUBR7IPImm (const uint32_t opcode, const ARMEncoding encoding)
1736 if (ConditionPassed(opcode))
1745 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1768 EmulateInstructionARM::EmulateSUBIPSPImm (const uint32_t opcode, const ARMEncoding encoding)
1788 if (ConditionPassed(opcode))
1797 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1822 EmulateInstructionARM::EmulateSUBSPImm (const uint32_t opcode, const ARMEncoding encoding)
1843 if (ConditionPassed(opcode))
1856 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
1859 Rd = Bits32(opcode, 11, 8);
1860 setflags = BitIsSet(opcode, 20);
1861 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
1863 return EmulateCMPImm(opcode, eEncodingT2);
1868 Rd = Bits32(opcode, 11, 8);
1870 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
1875 Rd = Bits32(opcode, 15, 12);
1876 setflags = BitIsSet(opcode, 20);
1877 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1881 return EmulateSUBSPcLrEtc (opcode, encoding);
1910 EmulateInstructionARM::EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding encoding)
1926 if (ConditionPassed(opcode, &conditional))
1941 Rt = Bits32(opcode, 15, 12);
1942 imm12 = Bits32(opcode, 11, 0);
1943 Rn = Bits32 (opcode, 19, 16);
1948 index = BitIsSet (opcode, 24);
1949 add = BitIsSet (opcode, 23);
1950 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
2013 EmulateInstructionARM::EmulateVPUSH (const uint32_t opcode, const ARMEncoding encoding)
2036 if (ConditionPassed(opcode, &conditional))
2050 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
2051 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2053 regs = Bits32(opcode, 7, 0) / 2;
2061 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
2062 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2063 regs = Bits32(opcode, 7, 0);
2110 EmulateInstructionARM::EmulateVPOP (const uint32_t opcode, const ARMEncoding encoding)
2132 if (ConditionPassed(opcode, &conditional))
2146 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
2147 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2149 regs = Bits32(opcode, 7, 0) / 2;
2157 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
2158 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2159 regs = Bits32(opcode, 7, 0);
2205 EmulateInstructionARM::EmulateSVC (const uint32_t opcode, const ARMEncoding encoding)
2218 if (ConditionPassed(opcode))
2229 imm32 = Bits32(opcode, 7, 0);
2234 imm32 = Bits32(opcode, 23, 0);
2252 EmulateInstructionARM::EmulateIT (const uint32_t opcode, const ARMEncoding encoding)
2260 m_it_session.InitIT(Bits32(opcode, 7, 0));
2265 EmulateInstructionARM::EmulateNop (const uint32_t opcode, const ARMEncoding encoding)
2273 EmulateInstructionARM::EmulateB (const uint32_t opcode, const ARMEncoding encoding)
2286 if (ConditionPassed(opcode))
2298 imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1);
2303 imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0));
2310 uint32_t S = Bit32(opcode, 26);
2311 uint32_t imm6 = Bits32(opcode, 21, 16);
2312 uint32_t J1 = Bit32(opcode, 13);
2313 uint32_t J2 = Bit32(opcode, 11);
2314 uint32_t imm11 = Bits32(opcode, 10, 0);
2323 uint32_t S = Bit32(opcode, 26);
2324 uint32_t imm10 = Bits32(opcode, 25, 16);
2325 uint32_t J1 = Bit32(opcode, 13);
2326 uint32_t J2 = Bit32(opcode, 11);
2327 uint32_t imm11 = Bits32(opcode, 10, 0);
2337 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
2354 EmulateInstructionARM::EmulateCB (const uint32_t opcode, const ARMEncoding encoding)
2366 uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success);
2381 imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1;
2382 nonzero = BitIsSet(opcode, 11);
2405 EmulateInstructionARM::EmulateTB (const uint32_t opcode, const ARMEncoding encoding)
2424 Rn = Bits32(opcode, 19, 16);
2425 Rm = Bits32(opcode, 3, 0);
2426 is_tbh = BitIsSet(opcode, 4);
2475 EmulateInstructionARM::EmulateADDImmThumb (const uint32_t opcode, const ARMEncoding encoding)
2491 if (ConditionPassed(opcode))
2504 d = Bits32 (opcode, 2, 0);
2505 n = Bits32 (opcode, 5, 3);
2507 imm32 = Bits32 (opcode, 8,6);
2513 d = Bits32 (opcode, 10, 8);
2514 n = Bits32 (opcode, 10, 8);
2516 imm32 = Bits32 (opcode, 7, 0);
2524 d = Bits32 (opcode, 11, 8);
2525 n = Bits32 (opcode, 19, 16);
2526 setflags = BitIsSet (opcode, 20);
2527 imm32 = ThumbExpandImm_C (opcode, APSR_C, carry_out);
2540 d = Bits32 (opcode, 11, 8);
2541 n = Bits32 (opcode, 19, 16);
2543 uint32_t i = Bit32 (opcode, 26);
2544 uint32_t imm3 = Bits32 (opcode, 14, 12);
2545 uint32_t imm8 = Bits32 (opcode, 7, 0);
2588 EmulateInstructionARM::EmulateADDImmARM (const uint32_t opcode, const ARMEncoding encoding)
2608 if (ConditionPassed(opcode))
2616 Rd = Bits32(opcode, 15, 12);
2617 Rn = Bits32(opcode, 19, 16);
2618 setflags = BitIsSet(opcode, 20);
2619 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2647 EmulateInstructionARM::EmulateADDReg (const uint32_t opcode, const ARMEncoding encoding)
2668 if (ConditionPassed(opcode))
2677 Rd = Bits32(opcode, 2, 0);
2678 Rn = Bits32(opcode, 5, 3);
2679 Rm = Bits32(opcode, 8, 6);
2685 Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
2686 Rm = Bits32(opcode, 6, 3);
2696 Rd = Bits32(opcode, 15, 12);
2697 Rn = Bits32(opcode, 19, 16);
2698 Rm = Bits32(opcode, 3, 0);
2699 setflags = BitIsSet(opcode, 20);
2700 shift_n = DecodeImmShiftARM(opcode, shift_t);
2738 EmulateInstructionARM::EmulateCMNImm (const uint32_t opcode, const ARMEncoding encoding)
2757 Rn = Bits32(opcode, 19, 16);
2758 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
2763 Rn = Bits32(opcode, 19, 16);
2764 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2788 EmulateInstructionARM::EmulateCMNReg (const uint32_t opcode, const ARMEncoding encoding)
2810 Rn = Bits32(opcode, 2, 0);
2811 Rm = Bits32(opcode, 5, 3);
2816 Rn = Bits32(opcode, 19, 16);
2817 Rm = Bits32(opcode, 3, 0);
2818 shift_n = DecodeImmShiftThumb(opcode, shift_t);
2824 Rn = Bits32(opcode, 19, 16);
2825 Rm = Bits32(opcode, 3, 0);
2826 shift_n = DecodeImmShiftARM(opcode, shift_t);
2858 EmulateInstructionARM::EmulateCMPImm (const uint32_t opcode, const ARMEncoding encoding)
2877 Rn = Bits32(opcode, 10, 8);
2878 imm32 = Bits32(opcode, 7, 0);
2881 Rn = Bits32(opcode, 19, 16);
2882 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
2887 Rn = Bits32(opcode, 19, 16);
2888 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2912 EmulateInstructionARM::EmulateCMPReg (const uint32_t opcode, const ARMEncoding encoding)
2934 Rn = Bits32(opcode, 2, 0);
2935 Rm = Bits32(opcode, 5, 3);
2940 Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
2941 Rm = Bits32(opcode, 6, 3);
2950 Rn = Bits32(opcode, 19, 16);
2951 Rm = Bits32(opcode, 3, 0);
2952 shift_n = DecodeImmShiftARM(opcode, shift_t);
2985 EmulateInstructionARM::EmulateASRImm (const uint32_t opcode, const ARMEncoding encoding)
3003 return EmulateShiftImm (opcode, encoding, SRType_ASR);
3011 EmulateInstructionARM::EmulateASRReg (const uint32_t opcode, const ARMEncoding encoding)
3027 return EmulateShiftReg (opcode, encoding, SRType_ASR);
3034 EmulateInstructionARM::EmulateLSLImm (const uint32_t opcode, const ARMEncoding encoding)
3052 return EmulateShiftImm (opcode, encoding, SRType_LSL);
3060 EmulateInstructionARM::EmulateLSLReg (const uint32_t opcode, const ARMEncoding encoding)
3076 return EmulateShiftReg (opcode, encoding, SRType_LSL);
3083 EmulateInstructionARM::EmulateLSRImm (const uint32_t opcode, const ARMEncoding encoding)
3101 return EmulateShiftImm (opcode, encoding, SRType_LSR);
3109 EmulateInstructionARM::EmulateLSRReg (const uint32_t opcode, const ARMEncoding encoding)
3125 return EmulateShiftReg (opcode, encoding, SRType_LSR);
3132 EmulateInstructionARM::EmulateRORImm (const uint32_t opcode, const ARMEncoding encoding)
3150 return EmulateShiftImm (opcode, encoding, SRType_ROR);
3158 EmulateInstructionARM::EmulateRORReg (const uint32_t opcode, const ARMEncoding encoding)
3174 return EmulateShiftReg (opcode, encoding, SRType_ROR);
3183 EmulateInstructionARM::EmulateRRX (const uint32_t opcode, const ARMEncoding encoding)
3201 return EmulateShiftImm (opcode, encoding, SRType_RRX);
3205 EmulateInstructionARM::EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type)
3215 if (ConditionPassed(opcode))
3239 Rd = Bits32(opcode, 2, 0);
3240 Rm = Bits32(opcode, 5, 3);
3242 imm5 = Bits32(opcode, 10, 6);
3250 Rd = Bits32(opcode, 11, 8);
3251 Rm = Bits32(opcode, 3, 0);
3252 setflags = BitIsSet(opcode, 20);
3253 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6);
3258 Rd = Bits32(opcode, 15, 12);
3259 Rm = Bits32(opcode, 3, 0);
3260 setflags = BitIsSet(opcode, 20);
3261 imm5 = Bits32(opcode, 11, 7);
3295 EmulateInstructionARM::EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type)
3304 if (ConditionPassed(opcode))
3313 Rd = Bits32(opcode, 2, 0);
3315 Rm = Bits32(opcode, 5, 3);
3319 Rd = Bits32(opcode, 11, 8);
3320 Rn = Bits32(opcode, 19, 16);
3321 Rm = Bits32(opcode, 3, 0);
3322 setflags = BitIsSet(opcode, 20);
3327 Rd = Bits32(opcode, 15, 12);
3328 Rn = Bits32(opcode, 3, 0);
3329 Rm = Bits32(opcode, 11, 8);
3330 setflags = BitIsSet(opcode, 20);
3369 EmulateInstructionARM::EmulateLDM (const uint32_t opcode, const ARMEncoding encoding)
3390 if (ConditionPassed(opcode, &conditional))
3400 n = Bits32 (opcode, 10, 8);
3401 registers = Bits32 (opcode, 7, 0);
3411 n = Bits32 (opcode, 19, 16);
3412 registers = Bits32 (opcode, 15, 0);
3414 wback = BitIsSet (opcode, 21);
3419 || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15)))
3433 n = Bits32 (opcode, 19, 16);
3434 registers = Bits32 (opcode, 15, 0);
3435 wback = BitIsSet (opcode, 21);
3515 EmulateInstructionARM::EmulateLDMDA (const uint32_t opcode, const ARMEncoding encoding)
3536 if (ConditionPassed(opcode))
3548 n = Bits32 (opcode, 19, 16);
3549 registers = Bits32 (opcode, 15, 0);
3550 wback = BitIsSet (opcode, 21);
3632 EmulateInstructionARM::EmulateLDMDB (const uint32_t opcode, const ARMEncoding encoding)
3652 if (ConditionPassed(opcode))
3662 n = Bits32 (opcode, 19, 16);
3663 registers = Bits32 (opcode, 15, 0);
3665 wback = BitIsSet (opcode, 21);
3670 || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15)))
3685 n = Bits32 (opcode, 19, 16);
3686 registers = Bits32 (opcode, 15, 0);
3687 wback = BitIsSet (opcode, 21);
3769 EmulateInstructionARM::EmulateLDMIB (const uint32_t opcode, const ARMEncoding encoding)
3788 if (ConditionPassed(opcode))
3798 n = Bits32 (opcode, 19, 16);
3799 registers = Bits32 (opcode, 15, 0);
3800 wback = BitIsSet (opcode, 21);
3882 EmulateInstructionARM::EmulateLDRRtRnImm (const uint32_t opcode, const ARMEncoding encoding)
3903 if (ConditionPassed(opcode))
3914 Rt = Bits32(opcode, 2, 0);
3915 Rn = Bits32(opcode, 5, 3);
3916 imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32);
3926 Rt = Bits32 (opcode, 10, 8);
3928 imm32 = Bits32 (opcode, 7, 0) << 2;
3940 Rt = Bits32 (opcode, 15, 12);
3941 Rn = Bits32 (opcode, 19, 16);
3942 imm32 = Bits32 (opcode, 11, 0);
3960 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
3964 Rt = Bits32 (opcode, 15, 12);
3965 Rn = Bits32 (opcode, 19, 16);
3966 imm32 = Bits32 (opcode, 7, 0);
3969 index = BitIsSet (opcode, 10);
3970 add = BitIsSet (opcode, 9);
3971 wback = BitIsSet (opcode, 8);
4039 EmulateInstructionARM::EmulateSTM (const uint32_t opcode, const ARMEncoding encoding)
4061 if (ConditionPassed(opcode))
4073 n = Bits32 (opcode, 10, 8);
4074 registers = Bits32 (opcode, 7, 0);
4086 n = Bits32 (opcode, 19, 16);
4087 registers = Bits32 (opcode, 15, 0);
4089 wback = BitIsSet (opcode, 21);
4103 n = Bits32 (opcode, 19, 16);
4104 registers = Bits32 (opcode, 15, 0);
4105 wback = BitIsSet (opcode, 21);
4193 EmulateInstructionARM::EmulateSTMDA (const uint32_t opcode, const ARMEncoding encoding)
4216 if (ConditionPassed(opcode))
4228 n = Bits32 (opcode, 19, 16);
4229 registers = Bits32 (opcode, 15, 0);
4230 wback = BitIsSet (opcode, 21);
4318 EmulateInstructionARM::EmulateSTMDB (const uint32_t opcode, const ARMEncoding encoding)
4342 if (ConditionPassed(opcode))
4354 if ((BitIsSet (opcode, 21)) && (Bits32 (opcode, 19, 16) == 13))
4359 n = Bits32 (opcode, 19, 16);
4360 registers = Bits32 (opcode, 15, 0);
4362 wback = BitIsSet (opcode, 21);
4373 if (BitIsSet (opcode, 21) && (Bits32 (opcode, 19, 16) == 13) && BitCount (Bits32 (opcode, 15, 0)) >= 2)
4378 n = Bits32 (opcode, 19, 16);
4379 registers = Bits32 (opcode, 15, 0);
4380 wback = BitIsSet (opcode, 21);
4469 EmulateInstructionARM::EmulateSTMIB (const uint32_t opcode, const ARMEncoding encoding)
4492 if (ConditionPassed(opcode))
4504 n = Bits32 (opcode, 19, 16);
4505 registers = Bits32 (opcode, 15, 0);
4506 wback = BitIsSet (opcode, 21);
4594 EmulateInstructionARM::EmulateSTRThumb (const uint32_t opcode, const ARMEncoding encoding)
4610 if (ConditionPassed(opcode))
4625 t = Bits32 (opcode, 2, 0);
4626 n = Bits32 (opcode, 5, 3);
4627 imm32 = Bits32 (opcode, 10, 6) << 2;
4637 t = Bits32 (opcode, 10, 8);
4639 imm32 = Bits32 (opcode, 7, 0) << 2;
4649 if (Bits32 (opcode, 19, 16) == 15)
4653 t = Bits32 (opcode, 15, 12);
4654 n = Bits32 (opcode, 19, 16);
4655 imm32 = Bits32 (opcode, 11, 0);
4671 if ((Bits32 (opcode, 19, 16) == 15)
4672 || (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)))
4676 t = Bits32 (opcode, 15, 12);
4677 n = Bits32 (opcode, 19, 16);
4678 imm32 = Bits32 (opcode, 7, 0);
4681 index = BitIsSet (opcode, 10);
4682 add = BitIsSet (opcode, 9);
4683 wback = BitIsSet (opcode, 8);
4754 EmulateInstructionARM::EmulateSTRRegister (const uint32_t opcode, const ARMEncoding encoding)
4775 if (ConditionPassed(opcode))
4794 t = Bits32 (opcode, 2, 0);
4795 n = Bits32 (opcode, 5, 3);
4796 m = Bits32 (opcode, 8, 6);
4810 if (Bits32 (opcode, 19, 16) == 15)
4814 t = Bits32 (opcode, 15, 12);
4815 n = Bits32 (opcode, 19, 16);
4816 m = Bits32 (opcode, 3, 0);
4825 shift_n = Bits32 (opcode, 5, 4);
4836 t = Bits32 (opcode, 15, 12);
4837 n = Bits32 (opcode, 19, 16);
4838 m = Bits32 (opcode, 3, 0);
4841 index = BitIsSet (opcode, 24);
4842 add = BitIsSet (opcode, 23);
4843 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
4846 uint32_t typ = Bits32 (opcode, 6, 5);
4847 uint32_t imm5 = Bits32 (opcode, 11, 7);
4944 EmulateInstructionARM::EmulateSTRBThumb (const uint32_t opcode, const ARMEncoding encoding)
4958 if (ConditionPassed(opcode))
4971 t = Bits32 (opcode, 2, 0);
4972 n = Bits32 (opcode, 5, 3);
4973 imm32 = Bits32 (opcode, 10, 6);
4983 if (Bits32 (opcode, 19, 16) == 15)
4987 t = Bits32 (opcode, 15, 12);
4988 n = Bits32 (opcode, 19, 16);
4989 imm32 = Bits32 (opcode, 11, 0);
5004 if (Bits32 (opcode, 19, 16) == 15)
5008 t = Bits32 (opcode, 15, 12);
5009 n = Bits32 (opcode, 19, 16);
5010 imm32 = Bits32 (opcode, 7, 0);
5013 index = BitIsSet (opcode, 10);
5014 add = BitIsSet (opcode, 9);
5015 wback = BitIsSet (opcode, 8);
5081 EmulateInstructionARM::EmulateSTRHRegister (const uint32_t opcode, const ARMEncoding encoding)
5098 if (ConditionPassed(opcode))
5115 t = Bits32 (opcode, 2, 0);
5116 n = Bits32 (opcode, 5, 3);
5117 m = Bits32 (opcode, 8, 6);
5133 t = Bits32 (opcode, 15, 12);
5134 n = Bits32 (opcode, 19, 16);
5135 m = Bits32 (opcode, 3, 0);
5146 shift_n = Bits32 (opcode, 5, 4);
5157 t = Bits32 (opcode, 15, 12);
5158 n = Bits32 (opcode, 19, 16);
5159 m = Bits32 (opcode, 3, 0);
5162 index = BitIsSet (opcode, 24);
5163 add = BitIsSet (opcode, 23);
5164 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
5261 EmulateInstructionARM::EmulateADCImm (const uint32_t opcode, const ARMEncoding encoding)
5281 if (ConditionPassed(opcode))
5289 Rd = Bits32(opcode, 11, 8);
5290 Rn = Bits32(opcode, 19, 16);
5291 setflags = BitIsSet(opcode, 20);
5292 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
5297 Rd = Bits32(opcode, 15, 12);
5298 Rn = Bits32(opcode, 19, 16);
5299 setflags = BitIsSet(opcode, 20);
5300 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5303 return EmulateSUBSPcLrEtc (opcode, encoding);
5330 EmulateInstructionARM::EmulateADCReg (const uint32_t opcode, const ARMEncoding encoding)
5351 if (ConditionPassed(opcode))
5360 Rd = Rn = Bits32(opcode, 2, 0);
5361 Rm = Bits32(opcode, 5, 3);
5367 Rd = Bits32(opcode, 11, 8);
5368 Rn = Bits32(opcode, 19, 16);
5369 Rm = Bits32(opcode, 3, 0);
5370 setflags = BitIsSet(opcode, 20);
5371 shift_n = DecodeImmShiftThumb(opcode, shift_t);
5376 Rd = Bits32(opcode, 15, 12);
5377 Rn = Bits32(opcode, 19, 16);
5378 Rm = Bits32(opcode, 3, 0);
5379 setflags = BitIsSet(opcode, 20);
5380 shift_n = DecodeImmShiftARM(opcode, shift_t);
5383 return EmulateSUBSPcLrEtc (opcode, encoding);
5417 EmulateInstructionARM::EmulateADR (const uint32_t opcode, const ARMEncoding encoding)
5432 if (ConditionPassed(opcode))
5440 Rd = Bits32(opcode, 10, 8);
5441 imm32 = ThumbImm8Scaled(opcode); // imm32 = ZeroExtend(imm8:'00', 32)
5446 Rd = Bits32(opcode, 11, 8);
5447 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
5448 add = (Bits32(opcode, 24, 21) == 0); // 0b0000 => ADD; 0b0101 => SUB
5454 Rd = Bits32(opcode, 15, 12);
5455 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5456 add = (Bits32(opcode, 24, 21) == 0x4); // 0b0100 => ADD; 0b0010 => SUB
5482 EmulateInstructionARM::EmulateANDImm (const uint32_t opcode, const ARMEncoding encoding)
5502 if (ConditionPassed(opcode))
5511 Rd = Bits32(opcode, 11, 8);
5512 Rn = Bits32(opcode, 19, 16);
5513 setflags = BitIsSet(opcode, 20);
5514 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
5517 return EmulateTSTImm(opcode, eEncodingT1);
5522 Rd = Bits32(opcode, 15, 12);
5523 Rn = Bits32(opcode, 19, 16);
5524 setflags = BitIsSet(opcode, 20);
5525 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
5528 return EmulateSUBSPcLrEtc (opcode, encoding);
5555 EmulateInstructionARM::EmulateANDReg (const uint32_t opcode, const ARMEncoding encoding)
5576 if (ConditionPassed(opcode))
5586 Rd = Rn = Bits32(opcode, 2, 0);
5587 Rm = Bits32(opcode, 5, 3);
5593 Rd = Bits32(opcode, 11, 8);
5594 Rn = Bits32(opcode, 19, 16);
5595 Rm = Bits32(opcode, 3, 0);
5596 setflags = BitIsSet(opcode, 20);
5597 shift_n = DecodeImmShiftThumb(opcode, shift_t);
5600 return EmulateTSTReg(opcode, eEncodingT2);
5605 Rd = Bits32(opcode, 15, 12);
5606 Rn = Bits32(opcode, 19, 16);
5607 Rm = Bits32(opcode, 3, 0);
5608 setflags = BitIsSet(opcode, 20);
5609 shift_n = DecodeImmShiftARM(opcode, shift_t);
5612 return EmulateSUBSPcLrEtc (opcode, encoding);
5647 EmulateInstructionARM::EmulateBICImm (const uint32_t opcode, const ARMEncoding encoding)
5667 if (ConditionPassed(opcode))
5676 Rd = Bits32(opcode, 11, 8);
5677 Rn = Bits32(opcode, 19, 16);
5678 setflags = BitIsSet(opcode, 20);
5679 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
5684 Rd = Bits32(opcode, 15, 12);
5685 Rn = Bits32(opcode, 19, 16);
5686 setflags = BitIsSet(opcode, 20);
5687 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
5691 return EmulateSUBSPcLrEtc (opcode, encoding);
5718 EmulateInstructionARM::EmulateBICReg (const uint32_t opcode, const ARMEncoding encoding)
5739 if (ConditionPassed(opcode))
5749 Rd = Rn = Bits32(opcode, 2, 0);
5750 Rm = Bits32(opcode, 5, 3);
5756 Rd = Bits32(opcode, 11, 8);
5757 Rn = Bits32(opcode, 19, 16);
5758 Rm = Bits32(opcode, 3, 0);
5759 setflags = BitIsSet(opcode, 20);
5760 shift_n = DecodeImmShiftThumb(opcode, shift_t);
5765 Rd = Bits32(opcode, 15, 12);
5766 Rn = Bits32(opcode, 19, 16);
5767 Rm = Bits32(opcode, 3, 0);
5768 setflags = BitIsSet(opcode, 20);
5769 shift_n = DecodeImmShiftARM(opcode, shift_t);
5773 return EmulateSUBSPcLrEtc (opcode, encoding);
5807 EmulateInstructionARM::EmulateLDRImmediateARM (const uint32_t opcode, const ARMEncoding encoding)
5826 if (ConditionPassed(opcode))
5844 t = Bits32 (opcode, 15, 12);
5845 n = Bits32 (opcode, 19, 16);
5846 imm32 = Bits32 (opcode, 11, 0);
5849 index = BitIsSet (opcode, 24);
5850 add = BitIsSet (opcode, 23);
5851 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
5946 EmulateInstructionARM::EmulateLDRRegister (const uint32_t opcode, const ARMEncoding encoding)
5969 if (ConditionPassed(opcode))
5987 t = Bits32 (opcode, 2, 0);
5988 n = Bits32 (opcode, 5, 3);
5989 m = Bits32 (opcode, 8, 6);
6005 t = Bits32 (opcode, 15, 12);
6006 n = Bits32 (opcode, 19, 16);
6007 m = Bits32 (opcode, 3, 0);
6016 shift_n = Bits32 (opcode, 5, 4);
6032 t = Bits32 (opcode, 15, 12);
6033 n = Bits32 (opcode, 19, 16);
6034 m = Bits32 (opcode, 3, 0);
6037 index = BitIsSet (opcode, 24);
6038 add = BitIsSet (opcode, 23);
6039 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
6042 uint32_t type = Bits32 (opcode, 6, 5);
6043 uint32_t imm5 = Bits32 (opcode, 11, 7);
6158 EmulateInstructionARM::EmulateLDRBImmediate (const uint32_t opcode, const ARMEncoding encoding)
6171 if (ConditionPassed(opcode))
6185 t = Bits32 (opcode, 2, 0);
6186 n = Bits32 (opcode, 5, 3);
6187 imm32 = Bits32 (opcode, 10, 6);
6200 t = Bits32 (opcode, 15, 12);
6201 n = Bits32 (opcode, 19, 16);
6202 imm32 = Bits32 (opcode, 11, 0);
6220 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
6224 t = Bits32 (opcode, 15, 12);
6225 n = Bits32 (opcode, 19, 16);
6226 imm32 = Bits32 (opcode, 7, 0);
6229 index = BitIsSet (opcode, 10);
6230 add = BitIsSet (opcode, 9);
6231 wback = BitIsSet (opcode, 8);
6294 EmulateInstructionARM::EmulateLDRBLiteral (const uint32_t opcode, const ARMEncoding encoding)
6306 if (ConditionPassed(opcode))
6316 t = Bits32 (opcode, 15, 12);
6317 imm32 = Bits32 (opcode, 11, 0);
6318 add = BitIsSet (opcode, 23);
6328 t = Bits32 (opcode, 15, 12);
6329 imm32 = Bits32 (opcode, 11, 0);
6330 add = BitIsSet (opcode, 23);
6374 EmulateInstructionARM::EmulateLDRBRegister (const uint32_t opcode, const ARMEncoding encoding)
6388 if (ConditionPassed(opcode))
6404 t = Bits32 (opcode, 2, 0);
6405 n = Bits32 (opcode, 5, 3);
6406 m = Bits32 (opcode, 8, 6);
6422 t = Bits32 (opcode, 15, 12);
6423 n = Bits32 (opcode, 19, 16);
6424 m = Bits32 (opcode, 3, 0);
6433 shift_n = Bits32 (opcode, 5, 4);
6444 t = Bits32 (opcode, 15, 12);
6445 n = Bits32 (opcode, 19, 16);
6446 m = Bits32 (opcode, 3, 0);
6449 index = BitIsSet (opcode, 24);
6450 add = BitIsSet (opcode, 23);
6451 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
6454 uint32_t type = Bits32 (opcode, 6, 5);
6455 uint32_t imm5 = Bits32 (opcode, 11, 7);
6531 EmulateInstructionARM::EmulateLDRHImmediate (const uint32_t opcode, const ARMEncoding encoding)
6549 if (ConditionPassed(opcode))
6563 t = Bits32 (opcode, 2, 0);
6564 n = Bits32 (opcode, 5, 3);
6565 imm32 = Bits32 (opcode, 10, 6) << 1;
6578 t = Bits32 (opcode, 15, 12);
6579 n = Bits32 (opcode, 19, 16);
6580 imm32 = Bits32 (opcode, 11, 0);
6597 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
6601 t = Bits32 (opcode, 15, 12);
6602 n = Bits32 (opcode, 19, 16);
6603 imm32 = Bits32 (opcode, 7, 0);
6606 index = BitIsSet (opcode, 10);
6607 add = BitIsSet (opcode, 9);
6608 wback = BitIsSet (opcode, 8);
6680 EmulateInstructionARM::EmulateLDRHLiteral (const uint32_t opcode, const ARMEncoding encoding)
6696 if (ConditionPassed(opcode))
6708 t = Bits32 (opcode, 15, 12);
6709 imm32 = Bits32 (opcode, 11, 0);
6710 add = BitIsSet (opcode, 23);
6720 uint32_t imm4H = Bits32 (opcode, 11, 8);
6721 uint32_t imm4L = Bits32 (opcode, 3, 0);
6724 t = Bits32 (opcode, 15, 12);
6726 add = BitIsSet (opcode, 23);
6788 EmulateInstructionARM::EmulateLDRHRegister (const uint32_t opcode, const ARMEncoding encoding)
6806 if (ConditionPassed(opcode))
6823 t = Bits32 (opcode, 2, 0);
6824 n = Bits32 (opcode, 5, 3);
6825 m = Bits32 (opcode, 8, 6);
6842 t = Bits32 (opcode, 15, 12);
6843 n = Bits32 (opcode, 19, 16);
6844 m = Bits32 (opcode, 3, 0);
6853 shift_n = Bits32 (opcode, 5, 4);
6863 t = Bits32 (opcode, 15, 12);
6864 n = Bits32 (opcode, 19, 16);
6865 m = Bits32 (opcode, 3, 0);
6868 index = BitIsSet (opcode, 24);
6869 add = BitIsSet (opcode, 23);
6870 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
6963 EmulateInstructionARM::EmulateLDRSBImmediate (const uint32_t opcode, const ARMEncoding encoding)
6976 if (ConditionPassed(opcode))
6992 t = Bits32 (opcode, 15, 12);
6993 n = Bits32 (opcode, 19, 16);
6994 imm32 = Bits32 (opcode, 11, 0);
7012 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
7016 t = Bits32 (opcode, 15, 12);
7017 n = Bits32 (opcode, 19, 16);
7018 imm32 = Bits32 (opcode, 7, 0);
7021 index = BitIsSet (opcode, 10);
7022 add = BitIsSet (opcode, 9);
7023 wback = BitIsSet (opcode, 8);
7027 && (BitIsClear (opcode, 10) || BitIsSet (opcode, 9) || BitIsSet (opcode, 8))))
7038 t = Bits32 (opcode, 15, 12);
7039 n = Bits32 (opcode, 19, 16);
7041 uint32_t imm4H = Bits32 (opcode, 11, 8);
7042 uint32_t imm4L = Bits32 (opcode, 3, 0);
7046 index = BitIsSet (opcode, 24);
7047 add = BitIsSet (opcode, 23);
7048 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
7112 EmulateInstructionARM::EmulateLDRSBLiteral (const uint32_t opcode, const ARMEncoding encoding)
7124 if (ConditionPassed(opcode))
7136 t = Bits32 (opcode, 15, 12);
7137 imm32 = Bits32 (opcode, 11, 0);
7138 add = BitIsSet (opcode, 23);
7149 t = Bits32 (opcode, 15, 12);
7150 uint32_t imm4H = Bits32 (opcode, 11, 8);
7151 uint32_t imm4L = Bits32 (opcode, 3, 0);
7153 add = BitIsSet (opcode, 23);
7202 EmulateInstructionARM::EmulateLDRSBRegister (const uint32_t opcode, const ARMEncoding encoding)
7216 if (ConditionPassed(opcode))
7232 t = Bits32 (opcode, 2, 0);
7233 n = Bits32 (opcode, 5, 3);
7234 m = Bits32 (opcode, 8, 6);
7251 t = Bits32 (opcode, 15, 12);
7252 n = Bits32 (opcode, 19, 16);
7253 m = Bits32 (opcode, 3, 0);
7262 shift_n = Bits32 (opcode, 5, 4);
7272 t = Bits32 (opcode, 15, 12);
7273 n = Bits32 (opcode, 19, 16);
7274 m = Bits32 (opcode, 3, 0);
7277 index = BitIsSet (opcode, 24);
7278 add = BitIsSet (opcode, 23);
7279 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
7360 EmulateInstructionARM::EmulateLDRSHImmediate (const uint32_t opcode, const ARMEncoding encoding)
7377 if (ConditionPassed(opcode))
7393 t = Bits32 (opcode, 15, 12);
7394 n = Bits32 (opcode, 19, 16);
7395 imm32 = Bits32 (opcode, 11, 0);
7413 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
7417 t = Bits32 (opcode, 15, 12);
7418 n = Bits32 (opcode, 19, 16);
7419 imm32 = Bits32 (opcode, 7, 0);
7422 index = BitIsSet (opcode, 10);
7423 add = BitIsSet (opcode, 9);
7424 wback = BitIsSet (opcode, 8);
7437 t = Bits32 (opcode, 15, 12);
7438 n = Bits32 (opcode, 19, 16);
7439 uint32_t imm4H = Bits32 (opcode, 11,8);
7440 uint32_t imm4L = Bits32 (opcode, 3, 0);
7444 index = BitIsSet (opcode, 24);
7445 add = BitIsSet (opcode, 23);
7446 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
7520 EmulateInstructionARM::EmulateLDRSHLiteral (const uint32_t opcode, const ARMEncoding encoding)
7536 if (ConditionPassed(opcode))
7548 t = Bits32 (opcode, 15, 12);
7549 imm32 = Bits32 (opcode, 11, 0);
7550 add = BitIsSet (opcode, 23);
7561 t = Bits32 (opcode, 15, 12);
7562 uint32_t imm4H = Bits32 (opcode, 11, 8);
7563 uint32_t imm4L = Bits32 (opcode, 3, 0);
7565 add = BitIsSet (opcode, 23);
7624 EmulateInstructionARM::EmulateLDRSHRegister (const uint32_t opcode, const ARMEncoding encoding)
7642 if (ConditionPassed(opcode))
7659 t = Bits32 (opcode, 2, 0);
7660 n = Bits32 (opcode, 5, 3);
7661 m = Bits32 (opcode, 8, 6);
7678 t = Bits32 (opcode, 15, 12);
7679 n = Bits32 (opcode, 19, 16);
7680 m = Bits32 (opcode, 3, 0);
7689 shift_n = Bits32 (opcode, 5, 4);
7700 t = Bits32 (opcode, 15, 12);
7701 n = Bits32 (opcode, 19, 16);
7702 m = Bits32 (opcode, 3, 0);
7705 index = BitIsSet (opcode, 24);
7706 add = BitIsSet (opcode, 23);
7707 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
7802 EmulateInstructionARM::EmulateSXTB (const uint32_t opcode, const ARMEncoding encoding)
7813 if (ConditionPassed(opcode))
7824 d = Bits32 (opcode, 2, 0);
7825 m = Bits32 (opcode, 5, 3);
7832 d = Bits32 (opcode, 11, 8);
7833 m = Bits32 (opcode, 3, 0);
7834 rotation = Bits32 (opcode, 5, 4) << 3;
7844 d = Bits32 (opcode, 15, 12);
7845 m = Bits32 (opcode, 3, 0);
7846 rotation = Bits32 (opcode, 11, 10) << 3;
7886 EmulateInstructionARM::EmulateSXTH (const uint32_t opcode, const ARMEncoding encoding)
7897 if (ConditionPassed(opcode))
7908 d = Bits32 (opcode, 2, 0);
7909 m = Bits32 (opcode, 5, 3);
7916 d = Bits32 (opcode, 11, 8);
7917 m = Bits32 (opcode, 3, 0);
7918 rotation = Bits32 (opcode, 5, 4) << 3;
7928 d = Bits32 (opcode, 15, 12);
7929 m = Bits32 (opcode, 3, 0);
7930 rotation = Bits32 (opcode, 11, 10) << 3;
7970 EmulateInstructionARM::EmulateUXTB (const uint32_t opcode, const ARMEncoding encoding)
7981 if (ConditionPassed(opcode))
7992 d = Bits32 (opcode, 2, 0);
7993 m = Bits32 (opcode, 5, 3);
8000 d = Bits32 (opcode, 11, 8);
8001 m = Bits32 (opcode, 3, 0);
8002 rotation = Bits32 (opcode, 5, 4) << 3;
8012 d = Bits32 (opcode, 15, 12);
8013 m = Bits32 (opcode, 3, 0);
8014 rotation = Bits32 (opcode, 11, 10) << 3;
8052 EmulateInstructionARM::EmulateUXTH (const uint32_t opcode, const ARMEncoding encoding)
8063 if (ConditionPassed(opcode))
8073 d = Bits32 (opcode, 2, 0);
8074 m = Bits32 (opcode, 5, 3);
8081 d = Bits32 (opcode, 11, 8);
8082 m = Bits32 (opcode, 3, 0);
8083 rotation = Bits32 (opcode, 5, 4) << 3;
8093 d = Bits32 (opcode, 15, 12);
8094 m = Bits32 (opcode, 3, 0);
8095 rotation = Bits32 (opcode, 11, 10) << 3;
8133 EmulateInstructionARM::EmulateRFE (const uint32_t opcode, const ARMEncoding encoding)
8150 if (ConditionPassed(opcode))
8162 n = Bits32 (opcode, 19, 16);
8163 wback = BitIsSet (opcode, 21);
8179 n = Bits32 (opcode, 19, 16);
8180 wback = BitIsSet (opcode, 21);
8196 n = Bits32 (opcode, 19, 16);
8199 wback = BitIsSet (opcode, 21);
8200 increment = BitIsSet (opcode, 23);
8201 wordhigher = (Bit32 (opcode, 24) == Bit32 (opcode, 23));
8281 EmulateInstructionARM::EmulateEORImm (const uint32_t opcode, const ARMEncoding encoding)
8301 if (ConditionPassed(opcode))
8310 Rd = Bits32(opcode, 11, 8);
8311 Rn = Bits32(opcode, 19, 16);
8312 setflags = BitIsSet(opcode, 20);
8313 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
8316 return EmulateTEQImm (opcode, eEncodingT1);
8321 Rd = Bits32(opcode, 15, 12);
8322 Rn = Bits32(opcode, 19, 16);
8323 setflags = BitIsSet(opcode, 20);
8324 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
8328 return EmulateSUBSPcLrEtc (opcode, encoding);
8355 EmulateInstructionARM::EmulateEORReg (const uint32_t opcode, const ARMEncoding encoding)
8376 if (ConditionPassed(opcode))
8386 Rd = Rn = Bits32(opcode, 2, 0);
8387 Rm = Bits32(opcode, 5, 3);
8393 Rd = Bits32(opcode, 11, 8);
8394 Rn = Bits32(opcode, 19, 16);
8395 Rm = Bits32(opcode, 3, 0);
8396 setflags = BitIsSet(opcode, 20);
8397 shift_n = DecodeImmShiftThumb(opcode, shift_t);
8400 return EmulateTEQReg (opcode, eEncodingT1);
8405 Rd = Bits32(opcode, 15, 12);
8406 Rn = Bits32(opcode, 19, 16);
8407 Rm = Bits32(opcode, 3, 0);
8408 setflags = BitIsSet(opcode, 20);
8409 shift_n = DecodeImmShiftARM(opcode, shift_t);
8413 return EmulateSUBSPcLrEtc (opcode, encoding);
8448 EmulateInstructionARM::EmulateORRImm (const uint32_t opcode, const ARMEncoding encoding)
8468 if (ConditionPassed(opcode))
8477 Rd = Bits32(opcode, 11, 8);
8478 Rn = Bits32(opcode, 19, 16);
8479 setflags = BitIsSet(opcode, 20);
8480 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
8483 return EmulateMOVRdImm (opcode, eEncodingT2);
8488 Rd = Bits32(opcode, 15, 12);
8489 Rn = Bits32(opcode, 19, 16);
8490 setflags = BitIsSet(opcode, 20);
8491 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
8494 return EmulateSUBSPcLrEtc (opcode, encoding);
8521 EmulateInstructionARM::EmulateORRReg (const uint32_t opcode, const ARMEncoding encoding)
8542 if (ConditionPassed(opcode))
8552 Rd = Rn = Bits32(opcode, 2, 0);
8553 Rm = Bits32(opcode, 5, 3);
8559 Rd = Bits32(opcode, 11, 8);
8560 Rn = Bits32(opcode, 19, 16);
8561 Rm = Bits32(opcode, 3, 0);
8562 setflags = BitIsSet(opcode, 20);
8563 shift_n = DecodeImmShiftThumb(opcode, shift_t);
8566 return EmulateMOVRdRm (opcode, eEncodingT3);
8571 Rd = Bits32(opcode, 15, 12);
8572 Rn = Bits32(opcode, 19, 16);
8573 Rm = Bits32(opcode, 3, 0);
8574 setflags = BitIsSet(opcode, 20);
8575 shift_n = DecodeImmShiftARM(opcode, shift_t);
8578 return EmulateSUBSPcLrEtc (opcode, encoding);
8612 EmulateInstructionARM::EmulateRSBImm (const uint32_t opcode, const ARMEncoding encoding)
8638 Rd = Bits32(opcode, 2, 0);
8639 Rn = Bits32(opcode, 5, 3);
8644 Rd = Bits32(opcode, 11, 8);
8645 Rn = Bits32(opcode, 19, 16);
8646 setflags = BitIsSet(opcode, 20);
8647 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
8652 Rd = Bits32(opcode, 15, 12);
8653 Rn = Bits32(opcode, 19, 16);
8654 setflags = BitIsSet(opcode, 20);
8655 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
8659 return EmulateSUBSPcLrEtc (opcode, encoding);
8684 EmulateInstructionARM::EmulateRSBReg (const uint32_t opcode, const ARMEncoding encoding)
8713 Rd = Bits32(opcode, 11, 8);
8714 Rn = Bits32(opcode, 19, 16);
8715 Rm = Bits32(opcode, 3, 0);
8716 setflags = BitIsSet(opcode, 20);
8717 shift_n = DecodeImmShiftThumb(opcode, shift_t);
8723 Rd = Bits32(opcode, 15, 12);
8724 Rn = Bits32(opcode, 19, 16);
8725 Rm = Bits32(opcode, 3, 0);
8726 setflags = BitIsSet(opcode, 20);
8727 shift_n = DecodeImmShiftARM(opcode, shift_t);
8731 return EmulateSUBSPcLrEtc (opcode, encoding);
8764 EmulateInstructionARM::EmulateRSCImm (const uint32_t opcode, const ARMEncoding encoding)
8790 Rd = Bits32(opcode, 15, 12);
8791 Rn = Bits32(opcode, 19, 16);
8792 setflags = BitIsSet(opcode, 20);
8793 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
8797 return EmulateSUBSPcLrEtc (opcode, encoding);
8823 EmulateInstructionARM::EmulateRSCReg (const uint32_t opcode, const ARMEncoding encoding)
8852 Rd = Bits32(opcode, 15, 12);
8853 Rn = Bits32(opcode, 19, 16);
8854 Rm = Bits32(opcode, 3, 0);
8855 setflags = BitIsSet(opcode, 20);
8856 shift_n = DecodeImmShiftARM(opcode, shift_t);
8860 return EmulateSUBSPcLrEtc (opcode, encoding);
8893 EmulateInstructionARM::EmulateSBCImm (const uint32_t opcode, const ARMEncoding encoding)
8919 Rd = Bits32(opcode, 11, 8);
8920 Rn = Bits32(opcode, 19, 16);
8921 setflags = BitIsSet(opcode, 20);
8922 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
8927 Rd = Bits32(opcode, 15, 12);
8928 Rn = Bits32(opcode, 19, 16);
8929 setflags = BitIsSet(opcode, 20);
8930 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
8934 return EmulateSUBSPcLrEtc (opcode, encoding);
8960 EmulateInstructionARM::EmulateSBCReg (const uint32_t opcode, const ARMEncoding encoding)
8989 Rd = Rn = Bits32(opcode, 2, 0);
8990 Rm = Bits32(opcode, 5, 3);
8996 Rd = Bits32(opcode, 11, 8);
8997 Rn = Bits32(opcode, 19, 16);
8998 Rm = Bits32(opcode, 3, 0);
8999 setflags = BitIsSet(opcode, 20);
9000 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9005 Rd = Bits32(opcode, 15, 12);
9006 Rn = Bits32(opcode, 19, 16);
9007 Rm = Bits32(opcode, 3, 0);
9008 setflags = BitIsSet(opcode, 20);
9009 shift_n = DecodeImmShiftARM(opcode, shift_t);
9013 return EmulateSUBSPcLrEtc (opcode, encoding);
9045 EmulateInstructionARM::EmulateSUBImmThumb (const uint32_t opcode, const ARMEncoding encoding)
9068 Rd = Bits32(opcode, 2, 0);
9069 Rn = Bits32(opcode, 5, 3);
9071 imm32 = Bits32(opcode, 8, 6); // imm32 = ZeroExtend(imm3, 32)
9074 Rd = Rn = Bits32(opcode, 10, 8);
9076 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
9079 Rd = Bits32(opcode, 11, 8);
9080 Rn = Bits32(opcode, 19, 16);
9081 setflags = BitIsSet(opcode, 20);
9082 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
9086 return EmulateCMPImm (opcode, eEncodingT2);
9090 return EmulateSUBSPImm (opcode, eEncodingT2);
9097 Rd = Bits32(opcode, 11, 8);
9098 Rn = Bits32(opcode, 19, 16);
9099 setflags = BitIsSet(opcode, 20);
9100 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
9104 return EmulateADR (opcode, eEncodingT2);
9108 return EmulateSUBSPImm (opcode, eEncodingT3);
9136 EmulateInstructionARM::EmulateSUBImmARM (const uint32_t opcode, const ARMEncoding encoding)
9162 Rd = Bits32(opcode, 15, 12);
9163 Rn = Bits32(opcode, 19, 16);
9164 setflags = BitIsSet(opcode, 20);
9165 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
9169 return EmulateADR (opcode, eEncodingA2);
9173 return EmulateSUBSPImm (opcode, eEncodingA1);
9177 return EmulateSUBSPcLrEtc (opcode, encoding);
9202 EmulateInstructionARM::EmulateTEQImm (const uint32_t opcode, const ARMEncoding encoding)
9217 if (ConditionPassed(opcode))
9225 Rn = Bits32(opcode, 19, 16);
9226 imm32 = ThumbExpandImm_C (opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
9231 Rn = Bits32(opcode, 19, 16);
9232 imm32 = ARMExpandImm_C (opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
9259 EmulateInstructionARM::EmulateTEQReg (const uint32_t opcode, const ARMEncoding encoding)
9275 if (ConditionPassed(opcode))
9284 Rn = Bits32(opcode, 19, 16);
9285 Rm = Bits32(opcode, 3, 0);
9286 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9291 Rn = Bits32(opcode, 19, 16);
9292 Rm = Bits32(opcode, 3, 0);
9293 shift_n = DecodeImmShiftARM(opcode, shift_t);
9327 EmulateInstructionARM::EmulateTSTImm (const uint32_t opcode, const ARMEncoding encoding)
9342 if (ConditionPassed(opcode))
9350 Rn = Bits32(opcode, 19, 16);
9351 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
9356 Rn = Bits32(opcode, 19, 16);
9357 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
9383 EmulateInstructionARM::EmulateTSTReg (const uint32_t opcode, const ARMEncoding encoding)
9399 if (ConditionPassed(opcode))
9408 Rn = Bits32(opcode, 2, 0);
9409 Rm = Bits32(opcode, 5, 3);
9414 Rn = Bits32(opcode, 19, 16);
9415 Rm = Bits32(opcode, 3, 0);
9416 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9421 Rn = Bits32(opcode, 19, 16);
9422 Rm = Bits32(opcode, 3, 0);
9423 shift_n = DecodeImmShiftARM(opcode, shift_t);
9456 EmulateInstructionARM::EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding encoding)
9476 if (ConditionPassed(opcode))
9488 d = Bits32 (opcode, 11, 8);
9489 m = Bits32 (opcode, 3, 0);
9490 setflags = BitIsSet (opcode, 20);
9493 shift_n = DecodeImmShiftThumb (opcode, shift_t);
9506 d = Bits32 (opcode, 15, 12);
9507 m = Bits32 (opcode, 3, 0);
9508 setflags = BitIsSet (opcode, 20);
9512 EmulateSUBSPcLrEtc (opcode, encoding);
9515 shift_n = DecodeImmShiftARM (opcode, shift_t);
9555 EmulateInstructionARM::EmulateADDRegShift (const uint32_t opcode, const ARMEncoding encoding)
9573 if (ConditionPassed(opcode))
9586 d = Bits32 (opcode, 15, 12);
9587 n = Bits32 (opcode, 19, 16);
9588 m = Bits32 (opcode, 3, 0);
9589 s = Bits32 (opcode, 11, 8);
9592 setflags = BitIsSet (opcode, 20);
9593 shift_t = DecodeRegShift (Bits32 (opcode, 6, 5));
9653 EmulateInstructionARM::EmulateSUBReg (const uint32_t opcode, const ARMEncoding encoding)
9673 if (ConditionPassed(opcode))
9686 d = Bits32 (opcode, 2, 0);
9687 n = Bits32 (opcode, 5, 3);
9688 m = Bits32 (opcode, 8, 6);
9701 d = Bits32 (opcode, 11, 8);
9702 n = Bits32 (opcode, 19, 16);
9703 m = Bits32 (opcode, 3, 0);
9704 setflags = BitIsSet (opcode, 20);
9707 shift_n = DecodeImmShiftThumb (opcode, shift_t);
9710 if ((d == 13) || ((d == 15) && BitIsClear (opcode, 20)) || (n == 15) || BadReg (m))
9718 d = Bits32 (opcode, 15, 12);
9719 n = Bits32 (opcode, 19, 16);
9720 m = Bits32 (opcode, 3, 0);
9721 setflags = BitIsSet (opcode, 20);
9725 EmulateSUBSPcLrEtc (opcode, encoding);
9728 shift_n = DecodeImmShiftARM (opcode, shift_t);
9780 EmulateInstructionARM::EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding)
9795 if (ConditionPassed(opcode))
9807 d = Bits32 (opcode, 11, 8);
9808 t = Bits32 (opcode, 15, 12);
9809 n = Bits32 (opcode, 19, 16);
9810 imm32 = Bits32 (opcode, 7, 0) << 2;
9824 d = Bits32 (opcode, 15, 12);
9825 t = Bits32 (opcode, 3, 0);
9826 n = Bits32 (opcode, 19, 16);
9887 EmulateInstructionARM::EmulateSTRBImmARM (const uint32_t opcode, const ARMEncoding encoding)
9900 if (ConditionPassed(opcode))
9914 t = Bits32 (opcode, 15, 12);
9915 n = Bits32 (opcode, 19, 16);
9916 imm32 = Bits32 (opcode, 11, 0);
9919 index = BitIsSet (opcode, 24);
9920 add = BitIsSet (opcode, 23);
9921 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
9983 EmulateInstructionARM::EmulateSTRImmARM (const uint32_t opcode, const ARMEncoding encoding)
9996 if (ConditionPassed(opcode))
10013 t = Bits32 (opcode, 15, 12);
10014 n = Bits32 (opcode, 19, 16);
10015 imm32 = Bits32 (opcode, 11, 0);
10018 index = BitIsSet (opcode, 24);
10019 add = BitIsSet (opcode, 23);
10020 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10095 EmulateInstructionARM::EmulateLDRDImmediate (const uint32_t opcode, const ARMEncoding encoding)
10109 if (ConditionPassed(opcode))
10125 t = Bits32 (opcode, 15, 12);
10126 t2 = Bits32 (opcode, 11, 8);
10127 n = Bits32 (opcode, 19, 16);
10128 imm32 = Bits32 (opcode, 7, 0) << 2;
10131 index = BitIsSet (opcode, 24);
10132 add = BitIsSet (opcode, 23);
10133 wback = BitIsSet (opcode, 21);
10149 t = Bits32 (opcode, 15, 12);
10153 n = Bits32 (opcode, 19, 16);
10154 imm32 = (Bits32 (opcode, 11, 8) << 4) | Bits32 (opcode, 3, 0);
10157 index = BitIsSet (opcode, 24);
10158 add = BitIsSet (opcode, 23);
10159 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10162 if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
10240 EmulateInstructionARM::EmulateLDRDRegister (const uint32_t opcode, const ARMEncoding encoding)
10254 if (ConditionPassed(opcode))
10269 t = Bits32 (opcode, 15, 12);
10273 n = Bits32 (opcode, 19, 16);
10274 m = Bits32 (opcode, 3, 0);
10277 index = BitIsSet (opcode, 24);
10278 add = BitIsSet (opcode, 23);
10279 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10282 if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
10367 EmulateInstructionARM::EmulateSTRDImm (const uint32_t opcode, const ARMEncoding encoding)
10381 if (ConditionPassed(opcode))
10396 t = Bits32 (opcode, 15, 12);
10397 t2 = Bits32 (opcode, 11, 8);
10398 n = Bits32 (opcode, 19, 16);
10399 imm32 = Bits32 (opcode, 7, 0) << 2;
10402 index = BitIsSet (opcode, 24);
10403 add = BitIsSet (opcode, 23);
10404 wback = BitIsSet (opcode, 21);
10419 t = Bits32 (opcode, 15, 12);
10424 n = Bits32 (opcode, 19, 16);
10425 imm32 = (Bits32 (opcode, 11, 8) << 4) | Bits32 (opcode, 3, 0);
10428 index = BitIsSet (opcode, 24);
10429 add = BitIsSet (opcode, 23);
10430 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10433 if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
10515 EmulateInstructionARM::EmulateSTRDReg (const uint32_t opcode, const ARMEncoding encoding)
10529 if (ConditionPassed(opcode))
10544 t = Bits32 (opcode, 15, 12);
10549 n = Bits32 (opcode, 19, 16);
10550 m = Bits32 (opcode, 3, 0);
10553 index = BitIsSet (opcode, 24);
10554 add = BitIsSet (opcode, 23);
10555 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10558 if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
10651 EmulateInstructionARM::EmulateVLDM (const uint32_t opcode, const ARMEncoding encoding)
10669 if (ConditionPassed(opcode))
10687 if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21))
10693 add = BitIsSet (opcode, 23);
10694 wback = BitIsSet (opcode, 21);
10697 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
10698 n = Bits32 (opcode, 19, 16);
10699 imm32 = Bits32 (opcode, 7, 0) << 2;
10702 regs = Bits32 (opcode, 7, 0) / 2;
10720 if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21))
10726 add = BitIsSet (opcode, 23);
10727 wback = BitIsSet (opcode, 21);
10728 d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22);
10729 n = Bits32 (opcode, 19, 16);
10732 imm32 = Bits32 (opcode, 7, 0) << 2;
10733 regs = Bits32 (opcode, 7, 0);
10842 EmulateInstructionARM::EmulateVSTM (const uint32_t opcode, const ARMEncoding encoding)
10861 if (ConditionPassed (opcode))
10879 if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21))
10885 add = BitIsSet (opcode, 23);
10886 wback = BitIsSet (opcode, 21);
10889 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
10890 n = Bits32 (opcode, 19, 16);
10891 imm32 = Bits32 (opcode, 7, 0) << 2;
10894 regs = Bits32 (opcode, 7, 0) / 2;
10912 if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21))
10918 add = BitIsSet (opcode, 23);
10919 wback = BitIsSet (opcode, 21);
10920 d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22);
10921 n = Bits32 (opcode, 19, 16);
10924 imm32 = Bits32 (opcode, 7, 0) << 2;
10925 regs = Bits32 (opcode, 7, 0);
11039 EmulateInstructionARM::EmulateVLDR (const uint32_t opcode, ARMEncoding encoding)
11056 if (ConditionPassed (opcode))
11070 add = BitIsSet (opcode, 23);
11071 imm32 = Bits32 (opcode, 7, 0) << 2;
11074 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11075 n = Bits32 (opcode, 19, 16);
11083 add = BitIsSet (opcode, 23);
11084 imm32 = Bits32 (opcode, 7, 0) << 2;
11087 d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22);
11088 n = Bits32 (opcode, 19, 16);
11169 EmulateInstructionARM::EmulateVSTR (const uint32_t opcode, ARMEncoding encoding)
11185 if (ConditionPassed (opcode))
11199 add = BitIsSet (opcode, 23);
11200 imm32 = Bits32 (opcode, 7, 0) << 2;
11203 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11204 n = Bits32 (opcode, 19, 16);
11216 add = BitIsSet (opcode, 23);
11217 imm32 = Bits32 (opcode, 7, 0) << 2;
11220 d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22);
11221 n = Bits32 (opcode, 19, 16);
11302 EmulateInstructionARM::EmulateVLD1Multiple (const uint32_t opcode, ARMEncoding encoding)
11317 if (ConditionPassed (opcode))
11346 uint32_t type = Bits32 (opcode, 11, 8);
11347 uint32_t align = Bits32 (opcode, 5, 4);
11381 ebytes = 1 << Bits32 (opcode, 7, 6);
11386 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11387 n = Bits32 (opcode, 19, 15);
11388 m = Bits32 (opcode, 3, 0);
11468 EmulateInstructionARM::EmulateVLD1Single (const uint32_t opcode, const ARMEncoding encoding)
11480 if (ConditionPassed (opcode))
11497 uint32_t size = Bits32 (opcode, 11, 10);
11498 uint32_t index_align = Bits32 (opcode, 7, 4);
11501 return EmulateVLD1SingleAll (opcode, encoding);
11558 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11559 n = Bits32 (opcode, 19, 16);
11560 m = Bits32 (opcode, 3, 0);
11644 EmulateInstructionARM::EmulateVST1Multiple (const uint32_t opcode, ARMEncoding encoding)
11659 if (ConditionPassed (opcode))
11677 uint32_t type = Bits32 (opcode, 11, 8);
11678 uint32_t align = Bits32 (opcode, 5, 4);
11716 ebytes = 1 << Bits32 (opcode,7, 6);
11721 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11722 n = Bits32 (opcode, 19, 16);
11723 m = Bits32 (opcode, 3, 0);
11807 EmulateInstructionARM::EmulateVST1Single (const uint32_t opcode, ARMEncoding encoding)
11819 if (ConditionPassed (opcode))
11836 uint32_t size = Bits32 (opcode, 11, 10);
11837 uint32_t index_align = Bits32 (opcode, 7, 4);
11898 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11899 n = Bits32 (opcode, 19, 16);
11900 m = Bits32 (opcode, 3, 0);
11969 EmulateInstructionARM::EmulateVLD1SingleAll (const uint32_t opcode, const ARMEncoding encoding)
11983 if (ConditionPassed (opcode))
12001 uint32_t size = Bits32 (opcode, 7, 6);
12002 if ((size == 3) || ((size == 0) && BitIsSet (opcode, 4)))
12008 if (BitIsClear (opcode, 5))
12014 if (BitIsClear (opcode, 4))
12020 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
12021 n = Bits32 (opcode, 19, 16);
12022 m = Bits32 (opcode, 3, 0);
12101 EmulateInstructionARM::EmulateSUBSPcLrEtc (const uint32_t opcode, const ARMEncoding encoding)
12109 case opcode of
12128 if (ConditionPassed (opcode))
12142 // n = 14; imm32 = ZeroExtend(imm8, 32); register_form = FALSE; opcode = �0010�; // = SUB
12144 imm32 = Bits32 (opcode, 7, 0);
12156 n = Bits32 (opcode, 19, 16);
12157 imm32 = ARMExpandImm (opcode);
12159 code = Bits32 (opcode, 24, 21);
12165 n = Bits32 (opcode, 19, 16);
12166 m = Bits32 (opcode, 3, 0);
12170 shift_n = DecodeImmShiftARM (opcode, shift_t);
12201 // case opcode of
12288 EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode, uint32_t arm_isa)
12513 if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value &&
12522 EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode, uint32_t arm_isa)
12578 // The next 5 opcode _must_ come before the if then instruction
12838 if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value &&
12950 EmulateInstructionARM::ConditionPassed (const uint32_t opcode, bool *is_conditional)
12962 const uint32_t cond = CurrentCond (opcode);
13035 EmulateInstructionARM::CurrentCond (const uint32_t opcode)
13043 return UnsignedBits(opcode, 31, 28);
13052 if (Bits32(opcode, 15, 12) == 0x0d && Bits32(opcode, 11, 7) != 0x0f)
13053 return Bits32(opcode, 11, 7);
13057 if (Bits32(opcode, 31, 27) == 0x1e &&
13058 Bits32(opcode, 15, 14) == 0x02 &&
13059 Bits32(opcode, 12, 12) == 0x00 &&
13060 Bits32(opcode, 25, 22) <= 0x0d)
13062 return Bits32(opcode, 25, 22);
13524 static ConstString opcode_key ("opcode");
13533 out_stream->Printf ("TestEmulation: Error reading opcode from test file.\n");