Target/X86/X86ISelLowering.cpp

845     setOperationAction(ISD::SRL, VT, Expand);
1093     setOperationAction(ISD::SRL,               MVT::v8i16, Custom);
1094     setOperationAction(ISD::SRL,               MVT::v16i8, Custom);
1104     setOperationAction(ISD::SRL,               MVT::v2i64, Custom);
1105     setOperationAction(ISD::SRL,               MVT::v4i32, Custom);
1166     setOperationAction(ISD::SRL,               MVT::v16i16, Custom);
1167     setOperationAction(ISD::SRL,               MVT::v32i8, Custom);
1251     setOperationAction(ISD::SRL,               MVT::v4i64, Custom);
1252     setOperationAction(ISD::SRL,               MVT::v8i32, Custom);
1393     setOperationAction(ISD::SRL,                MVT::v8i64, Custom);
1394     setOperationAction(ISD::SRL,                MVT::v16i32, Custom);
1510   setTargetDAGCombine(ISD::SRL);
6603         InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
8449     Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
9690   SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9736     if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
11348       Opcode = ISD::SRL;
12303     DAG.getNode(ISD::SRL, DL, MVT::i16,
12308     DAG.getNode(ISD::SRL, DL, MVT::i16,
12552     SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12555     SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12594         if (Op.getOpcode() == ISD::SRL)
12616         if (Op.getOpcode() == ISD::SRL) {
12618           SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12621           SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12626           return DAG.getNode(ISD::AND, dl, VT, SRL,
12637           SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12662         if (Op.getOpcode() == ISD::SRL) {
12664           SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12667           SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12672           return DAG.getNode(ISD::AND, dl, VT, SRL,
12683           SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12733     case ISD::SRL:
12840       case ISD::SRL:
12879     case ISD::SRL:
12913     if (Op.getOpcode() == ISD::SRL &&
13463   case ISD::SRL:
16414   Vec = DAG.getNode(ISD::SRL, dl, ScalarVT, Vec,
17802         (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17944   if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17946   if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
19160   case ISD::SRL:            return PerformShiftCombine(N, DAG, DCI, Subtarget);
19224   case ISD::SRL:
19270   case ISD::SRL: {