X86/Disassembler/X86Disassembler.cpp

10 // This file is part of the X86 Disassembler.
56 namespace X86 {
159 #define ENTRY(x) X86::x,
249   // By default sign-extend all X86 immediates based on their encoding.
257       // Special case those X86 instructions that use the imm8 as a set of
259       if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
260           Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
261           Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
262           Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
263           Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
264           Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
265           Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
266           Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
267           Opcode != X86::VINSERTPSrr)
288     mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
291     mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
294     mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
348     mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
393         baseReg = MCOperand::CreateReg(X86::x); break;
408     bool IndexIs128 = (Opcode == X86::VGATHERDPDrm ||
409                        Opcode == X86::VGATHERDPDYrm ||
410                        Opcode == X86::VGATHERQPDrm ||
411                        Opcode == X86::VGATHERDPSrm ||
412                        Opcode == X86::VGATHERQPSrm ||
413                        Opcode == X86::VPGATHERDQrm ||
414                        Opcode == X86::VPGATHERDQYrm ||
415                        Opcode == X86::VPGATHERQQrm ||
416                        Opcode == X86::VPGATHERDDrm ||
417                        Opcode == X86::VPGATHERQDrm);
418     bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
419                        Opcode == X86::VGATHERDPSYrm ||
420                        Opcode == X86::VGATHERQPSYrm ||
421                        Opcode == X86::VPGATHERQQYrm ||
422                        Opcode == X86::VPGATHERDDYrm ||
423                        Opcode == X86::VPGATHERQDYrm);
439         indexReg = MCOperand::CreateReg(X86::x); break;
465         baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
473       baseReg = MCOperand::CreateReg(X86::BX);
474       indexReg = MCOperand::CreateReg(X86::SI);
477       baseReg = MCOperand::CreateReg(X86::BX);
478       indexReg = MCOperand::CreateReg(X86::DI);
481       baseReg = MCOperand::CreateReg(X86::BP);
482       indexReg = MCOperand::CreateReg(X86::SI);
485       baseReg = MCOperand::CreateReg(X86::BP);
486       indexReg = MCOperand::CreateReg(X86::DI);
500         baseReg = MCOperand::CreateReg(X86::x); break;
519     X86::CS,
520     X86::SS,
521     X86::DS,
522     X86::ES,
523     X86::FS,
524     X86::GS
607   mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
690     if(mcInst.getOpcode() == X86::REP_PREFIX)
691       mcInst.setOpcode(X86::XRELEASE_PREFIX);
692     else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
693       mcInst.setOpcode(X86::XACQUIRE_PREFIX);