Target/SystemZ/SystemZFrameLowering.cpp

1 //===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
26     { SystemZ::R2D,  0x10 },
27     { SystemZ::R3D,  0x18 },
28     { SystemZ::R4D,  0x20 },
29     { SystemZ::R5D,  0x28 },
30     { SystemZ::R6D,  0x30 },
31     { SystemZ::R7D,  0x38 },
32     { SystemZ::R8D,  0x40 },
33     { SystemZ::R9D,  0x48 },
34     { SystemZ::R10D, 0x50 },
35     { SystemZ::R11D, 0x58 },
36     { SystemZ::R12D, 0x60 },
37     { SystemZ::R13D, 0x68 },
38     { SystemZ::R14D, 0x70 },
39     { SystemZ::R15D, 0x78 },
40     { SystemZ::F0D,  0x80 },
41     { SystemZ::F2D,  0x88 },
42     { SystemZ::F4D,  0x90 },
43     { SystemZ::F6D,  0x98 }
53   RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
79     for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
80       MRI.setPhysRegUsed(SystemZ::ArgGPRs[I]);
85     MRI.setPhysRegUsed(SystemZ::R11D);
90     MRI.setPhysRegUsed(SystemZ::R14D);
99     if (SystemZ::GR64BitRegClass.contains(Reg) && MRI.isPhysRegUsed(Reg)) {
100       MRI.setPhysRegUsed(SystemZ::R15D);
114   unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
139   unsigned HighGPR = SystemZ::R15D;
143     if (SystemZ::GR64BitRegClass.contains(Reg)) {
162     if (FirstGPR < SystemZ::NumArgGPRs) {
163       unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
176     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
183     MIB.addReg(SystemZ::R15D).addImm(StartOffset);
189       if (SystemZ::GR64BitRegClass.contains(Reg))
195       for (unsigned I = ZFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
196         addSavedGPR(MBB, MIB, TM, SystemZ::ArgGPRs[I], true);
202     if (SystemZ::FP64BitRegClass.contains(Reg)) {
205                                &SystemZ::FP64BitRegClass, TRI);
229     if (SystemZ::FP64BitRegClass.contains(Reg))
231                                 &SystemZ::FP64BitRegClass, TRI);
246     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
253     MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
293       Opcode = SystemZ::AGHI;
295       Opcode = SystemZ::AGFI;
330     if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
342       if (SystemZ::GR64BitRegClass.contains(Reg)) {
354     emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
367     BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
368       .addReg(SystemZ::R15D);
374     unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
383       I->addLiveIn(SystemZ::R11D);
391     if (SystemZ::FP64BitRegClass.contains(Reg)) {
393           (MBBI->getOpcode() == SystemZ::STD ||
394            MBBI->getOpcode() == SystemZ::STDY))
429     if (Opcode != SystemZ::LMG)
452     emitIncrement(MBB, MBBI, DL, SystemZ::R15D, StackSize, ZII);
511   case SystemZ::ADJCALLSTACKDOWN:
512   case SystemZ::ADJCALLSTACKUP: