Lines Matching refs:PPC
1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
41 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
44 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
47 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
346 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
459 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
460 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
461 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
462 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
511 setStackPointerRegisterToSaveRestore(PPC::X1);
512 setExceptionPointerRegister(PPC::X3);
513 setExceptionSelectorRegister(PPC::X4);
515 setStackPointerRegisterToSaveRestore(PPC::R1);
516 setExceptionPointerRegister(PPC::R3);
517 setExceptionSelectorRegister(PPC::R4);
568 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
569 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
720 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
736 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
758 "PPC only supports shuffles by bytes!");
775 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
784 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
794 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
796 "PPC only supports shuffles by bytes!");
830 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
859 bool PPC::isAllNegativeZeroVector(SDNode *N) {
875 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
885 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1164 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1179 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1215 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1364 DAG.getRegister(PPC::X2, MVT::i64));
1385 DAG.getRegister(PPC::X2, MVT::i64));
1428 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1441 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1451 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1461 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1462 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1468 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1469 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1474 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1484 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1485 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1491 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1512 DAG.getRegister(PPC::X2, MVT::i64));
1862 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1863 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1889 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1890 PPC::F8
1899 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1914 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1915 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2024 RC = &PPC::GPRCRegClass;
2027 RC = &PPC::F4RCRegClass;
2030 RC = &PPC::F8RCRegClass;
2036 RC = &PPC::VRRCRegClass;
2099 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2100 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2105 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2106 PPC::F8
2133 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2152 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2222 // TODO: add description of PPC stack frame format, or at least some docs.
2239 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2240 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2246 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2247 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2257 // entry to a function on PPC, the arguments start after the linkage area,
2328 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2367 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2390 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2417 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2419 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2437 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2492 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2518 // TODO: add description of PPC stack frame format, or at least some docs.
2536 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2537 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2540 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2541 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2547 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2548 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2609 // entry to a function on PPC, the arguments start after the linkage area,
2662 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2664 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2685 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2687 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2710 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2724 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2754 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2756 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2774 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2839 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2841 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3147 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3149 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3305 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3339 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3342 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3437 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3458 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3656 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3846 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3856 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3857 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3862 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3863 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4072 // when within range. The Darwin PPC ABI doc claims they also go in
4136 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4145 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4229 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4231 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4241 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4242 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4245 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4246 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4251 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4252 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4404 // when within range. The Darwin PPC ABI doc claims they also go in
4494 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4495 PPC::R12), Callee));
4587 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5062 // depend on the PPC behavior for oversized shift amounts.
5091 // depend on the PPC behavior for oversized shift amounts.
5469 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5470 PPC::isSplatShuffleMask(SVOp, 2) ||
5471 PPC::isSplatShuffleMask(SVOp, 4) ||
5472 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5473 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5474 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5475 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5476 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5477 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5478 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5479 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5480 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5488 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5489 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5490 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5491 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5492 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5493 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5494 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5495 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5496 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5652 DAG.getRegister(PPC::CR6, MVT::i32),
5924 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5925 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5939 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5943 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5945 BuildMI(BB, dl, TII->get(PPC::BCC))
5946 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5968 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5992 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5993 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6034 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6039 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6041 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6044 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6047 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6049 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6052 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6054 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6055 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6057 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6061 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6066 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6068 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6070 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6072 BuildMI(BB, dl, TII->get(PPC::STWCX))
6074 BuildMI(BB, dl, TII->get(PPC::BCC))
6075 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6082 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6164 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6165 .addReg(PPC::X2)
6176 BaseReg = PPCSubTarget.isPPC64() ? PPC::X1 : PPC::R1;
6178 BaseReg = PPCSubTarget.isPPC64() ? PPC::BP8 : PPC::BP;
6181 TII->get(PPCSubTarget.isPPC64() ? PPC::STD : PPC::STW))
6188 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6193 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6195 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6197 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6205 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6209 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6214 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6222 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6227 TII->get(PPC::PHI), DstReg)
6253 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6256 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6257 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6258 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6273 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6277 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6285 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6289 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6297 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6301 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6309 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6313 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6321 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6330 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6331 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6340 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6341 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6343 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6344 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6358 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6359 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6369 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6370 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6371 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6372 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6373 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6404 BuildMI(BB, dl, TII->get(PPC::BCC))
6420 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6424 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6425 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6426 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6427 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6428 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6429 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6430 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6431 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6433 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6434 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6435 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6436 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6437 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6438 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6439 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6440 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6442 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6443 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6444 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6445 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6446 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6447 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6448 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6449 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6451 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6452 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6453 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6454 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6455 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6456 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6457 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6458 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6460 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6461 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6462 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6463 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6464 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6465 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6466 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6467 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6469 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6470 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6471 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6472 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6473 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6474 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6475 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6476 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6478 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6480 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6482 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6484 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6487 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6488 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6489 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6528 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6530 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6532 BuildMI(BB, dl, TII->get(PPC::BCC))
6533 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6538 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6540 BuildMI(BB, dl, TII->get(PPC::BCC))
6541 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6542 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6547 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6554 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6555 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6560 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6584 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6585 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6601 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6636 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6641 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6643 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6646 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6649 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6651 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6653 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6656 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6658 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6659 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6662 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6664 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6666 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6670 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6672 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6674 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6676 BuildMI(BB, dl, TII->get(PPC::BCC))
6677 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6682 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6684 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6686 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6688 BuildMI(BB, dl, TII->get(PPC::BCC))
6689 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6690 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6695 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6702 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6704 } else if (MI->getOpcode() == PPC::FADDrtz) {
6714 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6717 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6720 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6721 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6724 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6727 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7494 PPC::Predicate CompOpc;
7498 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7501 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7504 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7507 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7513 DAG.getRegister(PPC::CR6, MVT::i32),
7643 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7644 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7647 return std::make_pair(0U, &PPC::G8RCRegClass);
7648 return std::make_pair(0U, &PPC::GPRCRegClass);
7651 return std::make_pair(0U, &PPC::F4RCRegClass);
7653 return std::make_pair(0U, &PPC::F8RCRegClass);
7656 return std::make_pair(0U, &PPC::VRRCRegClass);
7658 return std::make_pair(0U, &PPC::CRRCRegClass);
7672 PPC::GPRCRegClass.contains(R.first)) {
7675 PPC::sub_32, &PPC::G8RCRegClass),
7676 &PPC::G8RCRegClass);
7757 // FIXME: PPC does not allow r+i addressing modes for vectors!
7759 // PPC allows a sign-extended 16-bit immediate field.
7767 // PPC only support r+r,
7840 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7842 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7936 return PPC::createFastISel(FuncInfo, LibInfo);