Lines Matching refs:SrcVT

154     bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
738 MVT SrcVT = SrcEVT.getSimpleVT();
750 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
751 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
761 switch (SrcVT.SimpleTy) {
801 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
807 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
826 EVT SrcVT = TLI.getValueType(Src->getType(), true);
829 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
844 EVT SrcVT = TLI.getValueType(Src->getType(), true);
847 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
870 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
874 if (SrcVT == MVT::i32) {
894 if (SrcVT == MVT::i32) {
927 MVT SrcVT = SrcEVT.getSimpleVT();
929 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
930 SrcVT != MVT::i32 && SrcVT != MVT::i64)
951 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
953 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
955 SrcVT = MVT::i64;
960 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1021 MVT DstVT, SrcVT;
1035 if (!isTypeLegal(SrcTy, SrcVT))
1038 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1606 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1610 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1616 if (SrcVT == MVT::i8)
1618 else if (SrcVT == MVT::i16)
1630 if (SrcVT == MVT::i8)
1633 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1643 if (SrcVT == MVT::i8)
1645 else if (SrcVT == MVT::i16)
1677 EVT SrcVT = TLI.getValueType(Src->getType(), true);
1680 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1691 if (SrcVT == MVT::i64) {
1720 MVT SrcVT = SrcEVT.getSimpleVT();
1734 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))