CodeGen/SelectionDAG/DAGCombiner.cpp

910     else if (Opc == ISD::SRL)
1150   case ISD::SRL:                return visitSRL(N);
1233     case ISD::SRL:
1965     SDValue SRL = DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN,
1968     SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
1969     AddToWorkList(SRL.getNode());
2019     return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
2033         return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
2177       N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2213       N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2296       Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2326       Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2410   // For each of OP in SHL/SRL/SRA/AND...
2414   if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2843   if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2897   if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2921   if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2923   if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2962   // Make sure everything beyond the low halfword gets set to zero since the SRL
2982     Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res,
2995   if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
3018       if (N0.getOpcode() != ISD::SRL)
3040   } else { // Opc == ISD::SRL
3127                      DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt));
3297   if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3600        BinOpLHSVal->getOpcode() != ISD::SRL) ||
3725       N0.getOperand(0).getOpcode() == ISD::SRL &&
3746   if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3760         Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
3867           SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT,
3900       (N0.getOperand(0).getOpcode() == ISD::SRL ||
3925   // If the sign bit is known to be zero, switch this to a SRL.
3927     return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
3954     return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3970   if (N1C && N0.getOpcode() == ISD::SRL &&
3976     return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
3982       N0.getOperand(0).getOpcode() == ISD::SRL &&
3995                          DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT,
4016     if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
4018       SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT,
4033       return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4054       // could be set on input to the CTLZ node. If this bit is set, the SRL
4055       // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4056       // to an SRL/XOR pair, which is likely to simplify more.
4061         Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op,
4081       return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
4121   // However when after the source operand of SRL is optimized into AND, the SRL
4976   if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
5178   case ISD::SRL:
5191         return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
5220   } else if (Opc == ISD::SRL) {
5221     // Another special-case: SRL is basically zero-extending a narrower value.
5240   if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5254       // Because a SRL must be assumed to *need* to zero-extend the high bits
5256       // lowering of SRL and an sextload.
5416   if (N0.getOpcode() == ISD::SRL) {
5419         // We can turn this into an SRA iff the input to the SRL is already sign
5801         X = DAG.getNode(ISD::SRL, SDLoc(X),
6894   if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6897         N1.getOperand(0).getOpcode() == ISD::SRL))) {
6920     // SRL constant is equal to the log2 of the AND constant. The back-end is
6950           // Replace the uses of SRL with SETCC
8065     if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
8234     IVal = DAG.getNode(ISD::SRL, SDLoc(IVal), IVal.getValueType(), IVal,
10552         SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
10674       return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
10683       return DAG.getNode(ISD::SRL, DL, XType,
10690       SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0,