lib/CodeGen/RegAllocFast.cpp

72       unsigned VirtReg;         // Virtual register number.
78         : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {}
81         return TargetRegisterInfo::virtReg2Index(VirtReg);
167     int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
172     void killVirtReg(unsigned VirtReg);
174     void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
180     LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
181       return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
183     LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {
184       return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
190                                        unsigned VirtReg, unsigned Hint);
192                                        unsigned VirtReg, unsigned Hint);
201 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
203   int SS = StackSlotForVirtReg[VirtReg];
212   StackSlotForVirtReg[VirtReg] = FrameIdx;
247   assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&
256 void RAFast::killVirtReg(unsigned VirtReg) {
257   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
259   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
264 /// spillVirtReg - This method spills the value specified by VirtReg into the
266 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
267   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
269   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
278   assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
285     DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
287     const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
288     int FI = getStackSpaceFor(LRI->VirtReg, RC);
297       LiveDbgValueMap[LRI->VirtReg];
402   switch (unsigned VirtReg = PhysRegState[PhysReg]) {
406     spillVirtReg(MI, VirtReg);
418     switch (unsigned VirtReg = PhysRegState[Alias]) {
422       spillVirtReg(MI, VirtReg);
445   switch (unsigned VirtReg = PhysRegState[PhysReg]) {
451     DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
455     LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
456     assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
466     switch (unsigned VirtReg = PhysRegState[Alias]) {
475       LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
476       assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
487 /// that PhysReg is the proper container for VirtReg now.  The physical
491   DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "
493   PhysRegState[PhysReg] = LR.VirtReg;
499 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
500   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
501   assert(LRI != LiveVirtRegs.end() && "VirtReg disappeared");
506 /// allocVirtReg - Allocate a physical register for VirtReg.
510   const unsigned VirtReg = LRI->VirtReg;
512   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
515   const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
530       // That invalidates LRI, so run a new lookup for VirtReg.
531       return assignVirtToPhysReg(VirtReg, Hint);
546   DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
567     // That invalidates LRI, so run a new lookup for VirtReg.
568     return assignVirtToPhysReg(VirtReg, BestReg);
577   return assignVirtToPhysReg(VirtReg, *AO.begin());
580 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
583                       unsigned VirtReg, unsigned Hint) {
584   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
588   tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
592         MRI->hasOneNonDBGUse(VirtReg)) {
593       const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
601     // instruction defining VirtReg multiple times.
613 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
616                       unsigned VirtReg, unsigned Hint) {
617   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
621   tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
625     const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
626     int FrameIndex = getStackSpaceFor(VirtReg, RC);
627     DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
820             assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
832            assert(TargetRegisterInfo::isVirtualRegister(i->VirtReg) &&
836            assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map");