binutils/opcodes/ppc-opc.c

411   /* The SH field in an X or M form instruction.  */
412 #define SH RSO + 1
415 #define EVUIMM SH
418   /* The SH field in an MD form instruction.  This is split.  */
419 #define SH6 SH + 1
423   /* The SH field of the tlbwe instruction, which is optional.  */
541   /* SH field starting at bit position 16.  */
1137 /* The SH field in an MD form instruction.  This is split.  */
1351 /* An M_MASK with the SH and ME fields fixed.  */
1361 /* An MD_MASK with the SH field fixed.  */
1453 /* An X form tlb instruction with the SH field specified.  */
2984 { "rlwimi",  M(20,0),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
2985 { "rlimi",   M(20,0),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
2987 { "rlwimi.", M(20,1),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
2988 { "rlimi.",  M(20,1),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
2990 { "rotlwi",  MME(21,31,0), MMBME_MASK,	PPCCOM,		{ RA, RS, SH } },
2992 { "rlwinm",  M(21,0),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
2993 { "rlinm",   M(21,0),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
2994 { "rotlwi.", MME(21,31,1), MMBME_MASK,	PPCCOM,		{ RA,RS,SH } },
2996 { "rlwinm.", M(21,1),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
2997 { "rlinm.",  M(21,1),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3323 { "sliq",    XRC(31,184,0), X_MASK,	M601,		{ RA, RS, SH } },
3324 { "sliq.",   XRC(31,184,1), X_MASK,	M601,		{ RA, RS, SH } },
3404 { "slliq",   XRC(31,248,0), X_MASK,	M601,		{ RA, RS, SH } },
3405 { "slliq.",  XRC(31,248,1), X_MASK,	M601,		{ RA, RS, SH } },
4118 { "sriq",    XRC(31,696,0), X_MASK,	M601,		{ RA, RS, SH } },
4119 { "sriq.",   XRC(31,696,1), X_MASK,	M601,		{ RA, RS, SH } },
4142 { "srliq",   XRC(31,760,0), X_MASK,	M601,		{ RA, RS, SH } },
4143 { "srliq.",  XRC(31,760,1), X_MASK,	M601,		{ RA, RS, SH } },
4176 { "srawi",   XRC(31,824,0), X_MASK,	PPCCOM,		{ RA, RS, SH } },
4177 { "srai",    XRC(31,824,0), X_MASK,	PWRCOM,		{ RA, RS, SH } },
4178 { "srawi.",  XRC(31,824,1), X_MASK,	PPCCOM,		{ RA, RS, SH } },
4179 { "srai.",   XRC(31,824,1), X_MASK,	PWRCOM,		{ RA, RS, SH } },
4224 { "sraiq",   XRC(31,952,0), X_MASK,	M601,		{ RA, RS, SH } },
4225 { "sraiq.",  XRC(31,952,1), X_MASK,	M601,		{ RA, RS, SH } },