usr.sbin/bhyve/pci_passthru.c

109 	struct pci_io pi;
111 	bzero(&pi, sizeof(pi));
112 	pi.pi_sel = *sel;
113 	pi.pi_reg = reg;
114 	pi.pi_width = width;
116 	if (ioctl(pcifd, PCIOCREAD, &pi) < 0)
119 		return (pi.pi_data);
125 	struct pci_io pi;
127 	bzero(&pi, sizeof(pi));
128 	pi.pi_sel = *sel;
129 	pi.pi_reg = reg;
130 	pi.pi_width = width;
131 	pi.pi_data = data;
133 	(void)ioctl(pcifd, PCIOCWRITE, &pi);		/* XXX */
138 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
155 		pci_set_cfgdata8(pi, capoff + i, capdata[i]);
167 	struct pci_devinst *pi;
171 	pi = sc->psc_pi;
196 					pci_set_cfgdata32(pi, capptr, u32);
211 					pci_set_cfgdata32(pi, capptr, u32);
222 		pi->pi_msix.pba_bar =
224 		pi->pi_msix.pba_offset =
226 		pi->pi_msix.table_bar =
228 		pi->pi_msix.table_offset =
230 		pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
233 		table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
234 		pi->pi_msix.table = malloc(table_size);
235 		bzero(pi->pi_msix.table, table_size);
238 		for (i = 0; i < pi->pi_msix.table_count; i++) {
239 			pi->pi_msix.table[i].vector_control |=
253 		msiptr = passthru_add_msicap(pi, 1, origptr);
255 		sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
257 		pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
271 	struct pci_devinst *pi;
281 	pi = sc->psc_pi;
282 	offset -= pi->pi_msix.table_offset;
285 	if (index >= pi->pi_msix.table_count)
288 	entry = &pi->pi_msix.table[index];
319 	struct pci_devinst *pi;
326 	pi = sc->psc_pi;
327 	offset -= pi->pi_msix.table_offset;
330 	if (index >= pi->pi_msix.table_count)
333 	entry = &pi->pi_msix.table[index];
344 	if (pi->pi_msix.enabled) {
365 	struct pci_devinst *pi = sc->psc_pi;
367 	assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0);
379 	if (pi->pi_msix.pba_bar == pi->pi_msix.table_bar &&
380 	    ((pi->pi_msix.pba_offset - pi->pi_msix.table_offset) < 4096)) {
387 	table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
390 	idx = pi->pi_msix.table_bar;
391 	start = pi->pi_bar[idx].addr;
392 	remaining = pi->pi_bar[idx].size;
395 	if (pi->pi_msix.table_offset > 0) {
396 		len = pi->pi_msix.table_offset;
426 	struct pci_devinst *pi;
431 	pi = sc->psc_pi;
465 		error = pci_emul_alloc_pbar(pi, i, base, bartype,
471 		if (i == pci_msix_table_bar(pi)) {
479 				pi->pi_bar[i].addr, pi->pi_bar[i].size, base);
497 cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
503 	sc = pi->pi_arg;
522 passthru_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
552 	pi->pi_arg = sc;
553 	sc->psc_pi = pi;
556 	if ((error = cfginit(ctx, pi, bus, slot, func)) != 0)
604 passthru_cfgread(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
609 	sc = pi->pi_arg;
635 passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
641 	sc = pi->pi_arg;
653 		msicap_cfgwrite(pi, sc->psc_msi.capoff, coff, bytes, val);
656 			sc->psc_sel.pc_dev, sc->psc_sel.pc_func, pi->pi_msi.cpu,
657 			pi->pi_msi.vector, pi->pi_msi.msgnum);
666 		msixcap_cfgwrite(pi, sc->psc_msix.capoff, coff, bytes, val);
667 		if (pi->pi_msix.enabled) {
668 			msix_table_entries = pi->pi_msix.table_count;
673 						      pi->pi_msix.table[i].msg_data,
674 						      pi->pi_msix.table[i].vector_control,
675 						      pi->pi_msix.table[i].addr);
692 	if (sc->psc_msi.emulated && pci_msi_enabled(pi)) {
704 passthru_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
710 	sc = pi->pi_arg;
712 	if (baridx == pci_msix_table_bar(pi)) {
715 		assert(pi->pi_bar[baridx].type == PCIBAR_IO);
727 passthru_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
734 	sc = pi->pi_arg;
736 	if (baridx == pci_msix_table_bar(pi)) {
739 		assert(pi->pi_bar[baridx].type == PCIBAR_IO);