Lines Matching refs:block
38 #define XAUI_CONFIG0(block) NAE_REG(block, 4, 0x00)
39 #define XAUI_CONFIG1(block) NAE_REG(block, 4, 0x01)
40 #define XAUI_CONFIG2(block) NAE_REG(block, 4, 0x02)
41 #define XAUI_CONFIG3(block) NAE_REG(block, 4, 0x03)
43 #define XAUI_MAC_ADDR0_LO(block) NAE_REG(block, 4, 0x04)
44 #define XAUI_MAC_ADDR0_HI(block) NAE_REG(block, 4, 0x05)
46 #define XAUI_MAX_FRAME_LEN(block) NAE_REG(block, 4, 0x08)
47 #define XAUI_REVISION_LVL(block) NAE_REG(block, 4, 0x0b)
48 #define XAUI_MII_MGMT_CMD(block) NAE_REG(block, 4, 0x10)
49 #define XAUI_MII_MGMT_FIELD(block) NAE_REG(block, 4, 0x11)
50 #define XAUI_MII_MGMT_CFG(block) NAE_REG(block, 4, 0x12)
51 #define XAUI_MIIM_LINK_FALL_VEC(block) NAE_REG(block, 4, 0x13)
52 #define XAUI_MII_MGMT_IND(block) NAE_REG(block, 4, 0x14)
53 #define XAUI_STATS_MLR(block) NAE_REG(block, 4, 0x1f)
54 #define XAUI_STATS_TR64(block) NAE_REG(block, 4, 0x20)
55 #define XAUI_STATS_TR127(block) NAE_REG(block, 4, 0x21)
56 #define XAUI_STATS_TR255(block) NAE_REG(block, 4, 0x22)
57 #define XAUI_STATS_TR511(block) NAE_REG(block, 4, 0x23)
58 #define XAUI_STATS_TR1K(block) NAE_REG(block, 4, 0x24)
59 #define XAUI_STATS_TRMAX(block) NAE_REG(block, 4, 0x25)
60 #define XAUI_STATS_TRMGV(block) NAE_REG(block, 4, 0x26)
61 #define XAUI_STATS_RBYT(block) NAE_REG(block, 4, 0x27)
62 #define XAUI_STATS_RPKT(block) NAE_REG(block, 4, 0x28)
63 #define XAUI_STATS_RFCS(block) NAE_REG(block, 4, 0x29)
64 #define XAUI_STATS_RMCA(block) NAE_REG(block, 4, 0x2a)
65 #define XAUI_STATS_RBCA(block) NAE_REG(block, 4, 0x2b)
66 #define XAUI_STATS_RXCF(block) NAE_REG(block, 4, 0x2c)
67 #define XAUI_STATS_RXPF(block) NAE_REG(block, 4, 0x2d)
68 #define XAUI_STATS_RXUO(block) NAE_REG(block, 4, 0x2e)
69 #define XAUI_STATS_RALN(block) NAE_REG(block, 4, 0x2f)
70 #define XAUI_STATS_RFLR(block) NAE_REG(block, 4, 0x30)
71 #define XAUI_STATS_RCDE(block) NAE_REG(block, 4, 0x31)
72 #define XAUI_STATS_RCSE(block) NAE_REG(block, 4, 0x32)
73 #define XAUI_STATS_RUND(block) NAE_REG(block, 4, 0x33)
74 #define XAUI_STATS_ROVR(block) NAE_REG(block, 4, 0x34)
75 #define XAUI_STATS_RFRG(block) NAE_REG(block, 4, 0x35)
76 #define XAUI_STATS_RJBR(block) NAE_REG(block, 4, 0x36)
77 #define XAUI_STATS_TBYT(block) NAE_REG(block, 4, 0x38)
78 #define XAUI_STATS_TPKT(block) NAE_REG(block, 4, 0x39)
79 #define XAUI_STATS_TMCA(block) NAE_REG(block, 4, 0x3a)
80 #define XAUI_STATS_TBCA(block) NAE_REG(block, 4, 0x3b)
81 #define XAUI_STATS_TXPF(block) NAE_REG(block, 4, 0x3c)
82 #define XAUI_STATS_TDFR(block) NAE_REG(block, 4, 0x3d)
83 #define XAUI_STATS_TEDF(block) NAE_REG(block, 4, 0x3e)
84 #define XAUI_STATS_TSCL(block) NAE_REG(block, 4, 0x3f)
85 #define XAUI_STATS_TMCL(block) NAE_REG(block, 4, 0x40)
86 #define XAUI_STATS_TLCL(block) NAE_REG(block, 4, 0x41)
87 #define XAUI_STATS_TXCL(block) NAE_REG(block, 4, 0x42)
88 #define XAUI_STATS_TNCL(block) NAE_REG(block, 4, 0x43)
89 #define XAUI_STATS_TJBR(block) NAE_REG(block, 4, 0x46)
90 #define XAUI_STATS_TFCS(block) NAE_REG(block, 4, 0x47)
91 #define XAUI_STATS_TXCF(block) NAE_REG(block, 4, 0x48)
92 #define XAUI_STATS_TOVR(block) NAE_REG(block, 4, 0x49)
93 #define XAUI_STATS_TUND(block) NAE_REG(block, 4, 0x4a)
94 #define XAUI_STATS_TFRG(block) NAE_REG(block, 4, 0x4b)
95 #define XAUI_STATS_CAR1(block) NAE_REG(block, 4, 0x4c)
96 #define XAUI_STATS_CAR2(block) NAE_REG(block, 4, 0x4d)
97 #define XAUI_STATS_CAM1(block) NAE_REG(block, 4, 0x4e)
98 #define XAUI_STATS_CAM2(block) NAE_REG(block, 4, 0x4f)
99 #define XAUI_MAC_ADDR0_LO(block) NAE_REG(block, 4, 0x50)
100 #define XAUI_MAC_ADDR0_HI(block) NAE_REG(block, 4, 0x51)
101 #define XAUI_MAC_ADDR1_LO(block) NAE_REG(block, 4, 0x52)
102 #define XAUI_MAC_ADDR1_HI(block) NAE_REG(block, 4, 0x53)
103 #define XAUI_MAC_ADDR2_LO(block) NAE_REG(block, 4, 0x54)
104 #define XAUI_MAC_ADDR2_HI(block) NAE_REG(block, 4, 0x55)
105 #define XAUI_MAC_ADDR3_LO(block) NAE_REG(block, 4, 0x56)
106 #define XAUI_MAC_ADDR3_HI(block) NAE_REG(block, 4, 0x57)
107 #define XAUI_MAC_ADDR_MASK0_LO(block) NAE_REG(block, 4, 0x58)
108 #define XAUI_MAC_ADDR_MASK0_HI(block) NAE_REG(block, 4, 0x59)
109 #define XAUI_MAC_ADDR_MASK1_LO(block) NAE_REG(block, 4, 0x5a)
110 #define XAUI_MAC_ADDR_MASK1_HI(block) NAE_REG(block, 4, 0x5b)
111 #define XAUI_MAC_FILTER_CFG(block) NAE_REG(block, 4, 0x5c)
112 #define XAUI_HASHTBL_VEC_B31_0(block) NAE_REG(block, 4, 0x60)
113 #define XAUI_HASHTBL_VEC_B63_32(block) NAE_REG(block, 4, 0x61)
114 #define XAUI_HASHTBL_VEC_B95_64(block) NAE_REG(block, 4, 0x62)
115 #define XAUI_HASHTBL_VEC_B127_96(block) NAE_REG(block, 4, 0x63)
116 #define XAUI_HASHTBL_VEC_B159_128(block) NAE_REG(block, 4, 0x64)
117 #define XAUI_HASHTBL_VEC_B191_160(block) NAE_REG(block, 4, 0x65)
118 #define XAUI_HASHTBL_VEC_B223_192(block) NAE_REG(block, 4, 0x66)
119 #define XAUI_HASHTBL_VEC_B255_224(block) NAE_REG(block, 4, 0x67)
120 #define XAUI_HASHTBL_VEC_B287_256(block) NAE_REG(block, 4, 0x68)
121 #define XAUI_HASHTBL_VEC_B319_288(block) NAE_REG(block, 4, 0x69)
122 #define XAUI_HASHTBL_VEC_B351_320(block) NAE_REG(block, 4, 0x6a)
123 #define XAUI_HASHTBL_VEC_B383_352(block) NAE_REG(block, 4, 0x6b)
124 #define XAUI_HASHTBL_VEC_B415_384(block) NAE_REG(block, 4, 0x6c)
125 #define XAUI_HASHTBL_VEC_B447_416(block) NAE_REG(block, 4, 0x6d)
126 #define XAUI_HASHTBL_VEC_B479_448(block) NAE_REG(block, 4, 0x6e)
127 #define XAUI_HASHTBL_VEC_B511_480(block) NAE_REG(block, 4, 0x6f)
129 #define XAUI_NETIOR_XGMAC_MISC0(block) NAE_REG(block, 4, 0x76)
130 #define XAUI_NETIOR_RX_ABORT_DROP_COUNT(block) NAE_REG(block, 4, 0x77)
131 #define XAUI_NETIOR_MACCTRL_PAUSE_QUANTA(block) NAE_REG(block, 4, 0x78)
132 #define XAUI_NETIOR_MACCTRL_OPCODE(block) NAE_REG(block, 4, 0x79)
133 #define XAUI_NETIOR_MAC_DA_H(block) NAE_REG(block, 4, 0x7a)
134 #define XAUI_NETIOR_MAC_DA_L(block) NAE_REG(block, 4, 0x7b)
135 #define XAUI_NETIOR_XGMAC_STAT(block) NAE_REG(block, 4, 0x7c)
136 #define XAUI_NETIOR_XGMAC_CTRL3(block) NAE_REG(block, 4, 0x7d)
137 #define XAUI_NETIOR_XGMAC_CTRL2(block) NAE_REG(block, 4, 0x7e)
138 #define XAUI_NETIOR_XGMAC_CTRL1(block) NAE_REG(block, 4, 0x7f)