Lines Matching refs:nblock
139 nlm_nae_setup_rx_mode_xaui(uint64_t base, int nblock, int iface, int port_type,
150 nlm_write_nae_reg(base, XAUI_MAC_FILTER_CFG(nblock), val);
154 nlm_nae_setup_mac_addr_xaui(uint64_t base, int nblock, int iface,
158 XAUI_MAC_ADDR0_LO(nblock),
165 XAUI_MAC_ADDR0_HI(nblock),
170 XAUI_MAC_ADDR_MASK0_LO(nblock),
173 XAUI_MAC_ADDR_MASK0_HI(nblock),
176 nlm_nae_setup_rx_mode_xaui(base, nblock, iface,
186 nlm_config_xaui_mtu(uint64_t nae_base, int nblock,
193 XAUI_MAX_FRAME_LEN(nblock),
198 nlm_config_xaui(uint64_t nae_base, int nblock,
203 val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
205 nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
207 val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
209 nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
210 nlm_write_nae_reg(nae_base, XAUI_CONFIG0(nblock), 0xffffffff);
211 nlm_write_nae_reg(nae_base, XAUI_CONFIG0(nblock), 0);
218 nlm_write_nae_reg(nae_base, XAUI_CONFIG1(nblock), val);
221 nlm_config_xaui_mtu(nae_base, nblock, max_tx_frame_sz,
225 val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
236 nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
242 nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL2(nblock), val);
245 val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock));
248 nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock), val);