Lines Matching refs:bits
38 #define VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits) bVAL16(bits, 0)
39 #define VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits) bVAL8(bits, 48)
40 #define VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits) bVAL8(bits, 56)
46 #define VXGE_HAL_VPATH_TO_FUNC_MAP_CFG1_GET_CFG1(bits) bVAL5(bits, 3)
48 #define VXGE_HAL_DEBUG_ASSIGNMENTS_GET_VHLABEL(bits) bVAL5(bits, 3)
49 #define VXGE_HAL_DEBUG_ASSIGNMENTS_GET_VPLANE(bits) bVAL5(bits, 11)
50 #define VXGE_HAL_DEBUG_ASSIGNMENTS_GET_FUNC(bits) bVAL5(bits, 19)
52 #define VXGE_HAL_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits)\
53 bVAL3(bits, 5)
54 #define VXGE_HAL_VPLANE_ASSIGNMENTS_GET_VPLANE_ASSIGNMENTS(bits) \
55 bVAL5(bits, 3)
80 #define VXGE_HAL_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(bits) bVAL1(bits, 3)
82 #define VXGE_HAL_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(bits) bVAL32(bits, 0)
84 #define VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits)\
85 bVAL14(bits, 50)
87 #define VXGE_HAL_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(bits) bVAL17(bits, 0)
89 #define VXGE_HAL_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits)\
90 bVAL5(bits, 3)
92 #define VXGE_HAL_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits)\
93 bVAL15(bits, 17)
109 #define VXGE_HAL_LAG_CFG_GET_MODE(bits) bVAL2(bits, 6)
110 #define VXGE_HAL_LAG_TX_CFG_GET_DISTRIB_ALG_SEL(bits) bVAL2(bits, 6)
112 #define VXGE_HAL_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits) bits
113 #define VXGE_HAL_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(bits) bits
115 #define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0(bits) bVAL15(bits, 1)
116 #define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1(bits) bVAL15(bits, 17)
117 #define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2(bits) bVAL15(bits, 33)
131 #define VXGE_HAL_RTDMA_BW_CTRL_GET_DESIRED_BW(bits) bVAL18(bits, 46)
151 #define VXGE_HAL_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(bits) bVAL48(bits, 0)
154 #define VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) bVAL48(bits, 0)
157 #define VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits)\
158 bVAL5(bits, 55)
160 #define VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits)\
161 bVAL2(bits, 62)
208 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE(bits) \
209 bVAL8(bits, 56)
214 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SUB_CODE(bits) \
215 bVAL8(bits, 48)
216 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SUB_SUB_CODE(bits) \
217 bVAL8(bits, 40)
218 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SKIP_BYTES(bits) \
219 bVAL32(bits, 24)
220 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_FW_UPGRADE_GET_TOTAL_STEPS(bits) \
221 bVAL32(bits, 0)
222 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_FW_UPGRADE_GET_COMPL_STEPS(bits) \
223 bVAL32(bits, 32)
225 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) bVAL48(bits, 0)
228 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(bits) bVAL11(bits, 0)
231 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_ETYPE(bits) bVAL11(bits, 0)
239 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(bits) bVAL1(bits, 3)
241 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(bits) bVAL1(bits, 7)
243 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(bits) bVAL16(bits, 8)
246 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN(bits) bVAL1(bits, 3)
248 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(bits)\
249 bVAL4(bits, 4)
251 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(bits)\
252 bVAL2(bits, 10)
257 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(bits)\
258 bVAL1(bits, 15)
260 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(bits)\
261 bVAL1(bits, 19)
263 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(bits)\
264 bVAL1(bits, 23)
266 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(bits)\
267 bVAL1(bits, 27)
269 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(bits)\
270 bVAL1(bits, 31)
272 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(bits)\
273 bVAL1(bits, 35)
275 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(bits)\
276 bVAL1(bits, 39)
278 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN(bits)\
279 bVAL1(bits, 43)
282 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(bits)\
283 bVAL1(bits, 3)
285 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA(bits)\
286 bVAL7(bits, 9)
290 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM(bits)\
291 bVAL8(bits, 0)
294 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(bits)\
295 bVAL1(bits, 8)
297 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA(bits)\
298 bVAL7(bits, 9)
301 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM(bits)\
302 bVAL8(bits, 16)
305 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(bits)\
306 bVAL1(bits, 24)
308 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA(bits)\
309 bVAL7(bits, 25)
312 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM(bits)\
313 bVAL8(bits, 0)
316 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(bits)\
317 bVAL1(bits, 8)
319 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA(bits)\
320 bVAL7(bits, 9)
323 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM(bits)\
324 bVAL8(bits, 16)
327 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(bits)\
328 bVAL1(bits, 24)
330 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA(bits)\
331 bVAL7(bits, 25)
335 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(bits)\
336 bVAL32(bits, 0)
339 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(bits)\
340 bVAL32(bits, 32)
344 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(bits)\
345 bVAL16(bits, 0)
348 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK(bits)\
349 bVAL16(bits, 16)
352 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK(bits)\
353 bVAL4(bits, 32)
356 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK(bits)\
357 bVAL4(bits, 36)
360 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK(bits)\
361 bVAL2(bits, 40)
363 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK(bits)\
364 bVAL2(bits, 42)
367 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY(bits) bVAL64(bits, 0)
370 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN(bits) bVAL1(bits, 3)
373 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN(bits) bVAL1(bits, 3)
376 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits)\
377 bVAL48(bits, 0)
380 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits)\
381 bVAL5(bits, 55)
384 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits)\
385 bVAL2(bits, 62)
388 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM(bits)\
389 bVAL8(bits, 0)
392 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN(bits)\
393 bVAL1(bits, 8)
395 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA(bits)\
396 bVAL7(bits, 9)
399 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM(bits)\
400 bVAL8(bits, 16)
403 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN(bits)\
404 bVAL1(bits, 24)
406 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA(bits)\
407 bVAL7(bits, 25)
410 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM(bits)\
411 bVAL8(bits, 32)
414 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN(bits)\
415 bVAL1(bits, 40)
417 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA(bits)\
418 bVAL7(bits, 41)
421 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM(bits)\
422 bVAL8(bits, 48)
425 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN(bits)\
426 bVAL1(bits, 56)
428 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA(bits)\
429 bVAL7(bits, 57)
457 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MEMO_ITEM_STATUS(bits) \
458 bVAL8(bits, 56)
464 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_GET_LAG_MODE(bits) \
465 bVAL3(bits, 61)
475 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PCI_ADDR(bits) bVAL16(bits, 16)
479 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_BYTE_COUNT(bits) bVAL8(bits, 40)
482 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_VH(bits) bVAL8(bits, 48)
484 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FUNCTION(bits) bVAL8(bits, 56)
487 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PCI_DATA(bits) bVAL32(bits, 32)
490 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_PCI_DATA(bits) bVAL32(bits, 32)
496 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_TYPE(bits) bVAL7(bits, 1)
506 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_DEST(bits) bVAL8(bits, 8)
510 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_SRC(bits) bVAL8(bits, 16)
512 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_SEQ_NUM(bits) bVAL32(bits, 16)
514 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_DATA(bits) bVAL16(bits, 48)
525 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_PRIORITY(bits) bVAL3(bits, 45)
526 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MIN_BW(bits) bVAL8(bits, 48)
527 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MAX_BW(bits) bVAL8(bits, 56)
534 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_TX_PRIORITY(bits) bVAL3(bits, 21)
535 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_TX_MIN_BW(bits) bVAL8(bits, 24)
536 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_TX_MAX_BW(bits) bVAL8(bits, 32)
542 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_NUM_FUNC(bits) bVAL8(bits, 32)
543 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FUNC_MODE(bits) bVAL8(bits, 56)
558 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits)\
559 bVAL8(bits, 0)
561 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits)\
562 bVAL8(bits, 8)
564 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits) bVAL16(bits, 16)
567 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits)\
568 bVAL8(bits, 32)
570 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits)\
571 bVAL8(bits, 40)
573 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits)\
574 bVAL16(bits, 48)
577 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_DAY(bits)\
578 bVAL8(bits, 0)
580 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MONTH(bits)\
581 bVAL8(bits, 8)
583 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_YEAR(bits)\
584 bVAL16(bits, 16)
587 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MAJOR(bits)\
588 bVAL8(bits, 32)
590 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MINOR(bits)\
591 bVAL8(bits, 40)
593 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_BUILD(bits)\
594 bVAL16(bits, 48)
601 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_API_VER(bits) \
602 vxge_bVALn(bits, 0, 8)
604 #define VXGE_HAL_ASIC_NTWK_VP_CTRL_GET_XMACJ_SHOW_PORT_INFO(bits)\
605 bVAL1(bits, 55)
606 #define VXGE_HAL_ASIC_NTWK_VP_CTRL_GET_XMACJ_PORT_NUM(bits) bVAL1(bits, 63)
608 #define VXGE_HAL_SRPCIM_TO_VPATH_ALARM_REG_GET_ALARM(bits) bVAL17(bits, 0)
610 #define VXGE_HAL_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(bits) bVAL16(bits, 48)
611 #define VXGE_HAL_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(bits)\
612 bVAL32(bits, 32)
613 #define VXGE_HAL_RXD_RETURNED_GET_RXD_RETURNED(bits) bVAL16(bits, 48)
614 #define VXGE_HAL_PRC_RXD_DOORBELL_GET_NEW_QW_CNT(bits) bVAL16(bits, 48)
615 #define VXGE_HAL_PRC_CFG6_GET_RXD_SPAT(bits) bVAL9(bits, 36)
616 #define VXGE_HAL_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(bits) bVAL32(bits, 0)
617 #define VXGE_HAL_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(bits) bVAL32(bits, 0)
618 #define VXGE_HAL_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(bits) bVAL32(bits, 0)
619 #define VXGE_HAL_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(bits) (bits)
620 #define VXGE_HAL_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(bits) (bits)
621 #define VXGE_HAL_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(bits) bVAL32(bits, 32)
622 #define VXGE_HAL_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(bits) bVAL32(bits, 32)
623 #define VXGE_HAL_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(bits)\
624 bVAL32(bits, 0)
625 #define VXGE_HAL_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(bits)\
626 bVAL32(bits, 32)
627 #define VXGE_HAL_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(bits)\
628 bVAL32(bits, 0)
629 #define VXGE_HAL_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(bits)\
630 bVAL32(bits, 32)
631 #define VXGE_HAL_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(bits)\
632 bVAL32(bits, 0)
633 #define VXGE_HAL_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(bits)\
634 bVAL32(bits, 32)
636 VXGE_HAL_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(bits)\
637 bVAL16(bits, 48)
638 #define VXGE_HAL_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(bits) bVAL16(bits, 0)
639 #define VXGE_HAL_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(bits) bVAL16(bits, 16)
640 #define VXGE_HAL_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(bits) bVAL16(bits, 32)
641 #define VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(bits) bVAL16(bits, 0)
642 #define VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(bits)\
643 bVAL16(bits, 16)
644 #define VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(bits) bVAL16(bits, 32)
718 #define VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(bits) bVAL5(bits, 19)
721 #define VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(bits) bVAL5(bits, 7)
724 #define VXGE_HAL_MDIO_MGR_ACCESS_GET_PORT_DATA(bits) bVAL16(bits, 32)
726 #define VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(bits) bVAL32(bits, 0)
727 #define VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(bits) bVAL32(bits, 32)
729 VXGE_HAL_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(bits)\
730 bVAL32(bits, 32)
732 VXGE_HAL_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(bits)\
733 bVAL32(bits, 32)
735 VXGE_HAL_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits)\
736 bVAL32(bits, 32)
737 #define VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(bits) bVAL32(bits, 0)
738 #define VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(bits) bVAL32(bits, 32)
739 #define VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(bits) bVAL32(bits, 0)
740 #define VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(bits) bVAL32(bits, 32)
741 #define VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(bits) bVAL32(bits, 0)
742 #define VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(bits) bVAL32(bits, 32)
743 #define VXGE_HAL_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(bits) bVAL32(bits, 32)
744 #define VXGE_HAL_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(bits) bVAL32(bits, 32)
746 #define VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_MSG(bits) bVAL32(bits, 0)
747 #define VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_CPL(bits) bVAL32(bits, 32)
748 #define VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT0(bits) bVAL32(bits, 0)
749 #define VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT1(bits) bVAL32(bits, 32)
750 #define VXGE_HAL_DEBUG_STATS2_GET_RSTDROP_CLIENT2(bits) bVAL32(bits, 0)
751 #define VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_PH(bits) bVAL16(bits, 0)
752 #define VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(bits) bVAL16(bits, 16)
753 #define VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(bits) bVAL16(bits, 32)
754 #define VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_PD(bits) bVAL16(bits, 0)
755 #define VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(bits) bVAL16(bits, 16)
756 #define VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(bits) bVAL16(bits, 32)
758 #define VXGE_HAL_ORP_LRO_EVENTS_GET_ORP_LRO_EVENTS(bits) (bits)
759 #define VXGE_HAL_ORP_BS_EVENTS_GET_ORP_BS_EVENTS(bits) (bits)
760 #define VXGE_HAL_ORP_IWARP_EVENTS_GET_ORP_IWARP_EVENTS(bits) (bits)
761 #define VXGE_HAL_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(bits)\
762 bVAL32(bits, 32)
764 #define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(bits)\
765 bVAL8(bits, 0)
766 #define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(bits)\
767 bVAL8(bits, 8)
768 #define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(bits)\
769 bVAL8(bits, 16)
771 #define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(bits)\
772 bVAL8(bits, 0)
773 #define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(bits)\
774 bVAL8(bits, 8)
775 #define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(bits)\
776 bVAL8(bits, 16)