Lines Matching refs:BIT_7
183 #define BIT_7 (1 << 7)
301 #define PCI_EXT_PATCH_3 BIT_7
365 #define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */
795 #define CS_ST_SW_IRQ BIT_7 /* Set IRQ SW Request */
808 #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */
838 #define Y2_IS_PSM_ACK BIT_7 /* PSM Ack (Yukon Optima) */
932 #define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */
986 #define TST_FRC_DPERR_MR BIT_7 /* force DATAPERR on MST RD */
1071 #define TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */
1107 #define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */
1229 #define WOL_CTL_ENA_PME_ON_PATTERN BIT_7
1250 #define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */
1350 #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
1357 #define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */
1381 #define PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */
1453 #define PHY_M_IS_FIFO_ERROR BIT_7 /* FIFO Overflow/Underrun Error */
1476 #define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/
1502 #define PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */
1563 #define PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */
1831 #define GM_GPCR_GIGS_ENA BIT_7 /* Gigabit Speed (1000 Mbps) */
1914 #define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */
1972 #define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
2070 #define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */