Lines Matching refs:BIT_15
175 #define BIT_15 (1 << 15)
278 #define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */
331 #define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */
787 #define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */
999 #define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */
1098 #define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */
1221 #define WOL_CTL_LINK_CHG_OCC BIT_15
1343 #define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */
1399 #define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */
1409 #define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */
1421 #define PHY_M_PS_SPEED_1000 BIT_15 /* 10 = 1000 Mbps */
1440 #define PHY_M_PS_DTE_DETECT BIT_15 /* Data Terminal Equipment (DTE) Detected */
1445 #define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */
1465 #define PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */
1498 #define PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */
1555 #define PHY_M_FC_AUTO_SEL BIT_15 /* Fiber/Copper Auto Sel. Dis. */
1568 #define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */
1569 #define PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */
1810 #define GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */
1824 #define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */
1845 #define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */
1856 #define GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */
2062 #define GMC_SEC_RST BIT_15 /* MAC SEC RST */
2093 #define GPC_ANEG_2 BIT_15 /* ANEG[2] */