dev/msk/if_msk.c

3481 		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3486 		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3979 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3980 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3981 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
4003 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
4004 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
4005 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
4024 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);
4198 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
4199 	val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4202 			CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4204 			val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4223 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4259 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),