dev/e1000/e1000_nvm.c

47 	struct e1000_nvm_info *nvm = &hw->nvm;
51 	nvm->ops.init_params = e1000_null_ops_generic;
52 	nvm->ops.acquire = e1000_null_ops_generic;
53 	nvm->ops.read = e1000_null_read_nvm;
54 	nvm->ops.release = e1000_null_nvm_generic;
55 	nvm->ops.reload = e1000_reload_nvm_generic;
56 	nvm->ops.update = e1000_null_ops_generic;
57 	nvm->ops.valid_led_default = e1000_null_led_default;
58 	nvm->ops.validate = e1000_null_ops_generic;
59 	nvm->ops.write = e1000_null_write_nvm;
114 	usec_delay(hw->nvm.delay_usec);
129 	usec_delay(hw->nvm.delay_usec);
144 	struct e1000_nvm_info *nvm = &hw->nvm;
151 	if (nvm->type == e1000_nvm_eeprom_microwire)
154 	if (nvm->type == e1000_nvm_eeprom_spi)
166 		usec_delay(nvm->delay_usec);
292 	struct e1000_nvm_info *nvm = &hw->nvm;
297 	if (nvm->type == e1000_nvm_eeprom_microwire) {
301 		usec_delay(nvm->delay_usec);
309 		usec_delay(nvm->delay_usec);
312 	} else if (nvm->type == e1000_nvm_eeprom_spi) {
317 		usec_delay(nvm->delay_usec);
321 		usec_delay(nvm->delay_usec);
338 	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
342 	} else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
378 	struct e1000_nvm_info *nvm = &hw->nvm;
384 	if (nvm->type == e1000_nvm_eeprom_microwire) {
391 	} else if (nvm->type == e1000_nvm_eeprom_spi) {
407 						 hw->nvm.opcode_bits);
437 	struct e1000_nvm_info *nvm = &hw->nvm;
448 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
450 		DEBUGOUT("nvm parameter(s) out of bounds\n");
454 	ret_val = nvm->ops.acquire(hw);
464 	if ((nvm->address_bits == 8) && (offset >= 128))
468 	e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
469 	e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
481 	nvm->ops.release(hw);
498 	struct e1000_nvm_info *nvm = &hw->nvm;
508 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
510 		DEBUGOUT("nvm parameter(s) out of bounds\n");
514 	ret_val = nvm->ops.acquire(hw);
524 		e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
526 					nvm->address_bits);
536 	nvm->ops.release(hw);
552 	struct e1000_nvm_info *nvm = &hw->nvm;
561 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
563 		DEBUGOUT("nvm parameter(s) out of bounds\n");
597 	struct e1000_nvm_info *nvm = &hw->nvm;
606 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
608 		DEBUGOUT("nvm parameter(s) out of bounds\n");
615 		ret_val = nvm->ops.acquire(hw);
621 			nvm->ops.release(hw);
629 					 nvm->opcode_bits);
636 		if ((nvm->address_bits == 8) && (offset >= 128))
640 		e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
642 					 nvm->address_bits);
651 			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
657 		nvm->ops.release(hw);
678 	struct e1000_nvm_info *nvm = &hw->nvm;
689 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
691 		DEBUGOUT("nvm parameter(s) out of bounds\n");
695 	ret_val = nvm->ops.acquire(hw);
704 				 (u16)(nvm->opcode_bits + 2));
706 	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
712 					 nvm->opcode_bits);
715 					 nvm->address_bits);
740 				 (u16)(nvm->opcode_bits + 2));
742 	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
745 	nvm->ops.release(hw);
775 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
781 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
826 	ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
847 		ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
882 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
888 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
900 	ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
1153 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1186 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1194 	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);