drm2/radeon/rs400.c

64 	uint32_t tmp;
69 		tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
70 		if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
112 	uint32_t tmp;
115 	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
116 	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
117 	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
152 	tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
153 	tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
155 		WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
156 		tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
157 		WREG32(RADEON_BUS_CNTL, tmp);
159 		WREG32(RADEON_MC_AGP_LOCATION, tmp);
160 		tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
161 		WREG32(RADEON_BUS_CNTL, tmp);
164 	tmp = (u32)rdev->gart.table_addr & 0xfffff000;
165 	tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
167 	WREG32_MC(RS480_GART_BASE, tmp);
177 		tmp = RREG32_MC(RS690_MC_NB_CNTL);
178 		tmp &= ~(RS690_HIDE_MMCFG_BAR |
181 		WREG32_MC(RS690_MC_NB_CNTL, tmp);
199 	uint32_t tmp;
201 	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
202 	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
203 	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
237 	uint32_t tmp;
241 		tmp = RREG32(RADEON_MC_STATUS);
242 		if (tmp & RADEON_MC_IDLE) {
300 	uint32_t tmp;
302 	tmp = RREG32(RADEON_HOST_PATH_CNTL);
303 	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
304 	tmp = RREG32(RADEON_BUS_CNTL);
305 	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
306 	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
307 	seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
309 		tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
310 		seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
311 		tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
312 		seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
313 		tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
314 		seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
315 		tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
316 		seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
317 		tmp = RREG32(RS690_HDP_FB_LOCATION);
318 		seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
320 		tmp = RREG32(RADEON_AGP_BASE);
321 		seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
322 		tmp = RREG32(RS480_AGP_BASE_2);
323 		seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
324 		tmp = RREG32(RADEON_MC_AGP_LOCATION);
325 		seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
327 	tmp = RREG32_MC(RS480_GART_BASE);
328 	seq_printf(m, "GART_BASE 0x%08x\n", tmp);
329 	tmp = RREG32_MC(RS480_GART_FEATURE_ID);
330 	seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
331 	tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
332 	seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
333 	tmp = RREG32_MC(RS480_MC_MISC_CNTL);
334 	seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
335 	tmp = RREG32_MC(0x5F);
336 	seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
337 	tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
338 	seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
339 	tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
340 	seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
341 	tmp = RREG32_MC(0x3B);
342 	seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
343 	tmp = RREG32_MC(0x3C);
344 	seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
345 	tmp = RREG32_MC(0x30);
346 	seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
347 	tmp = RREG32_MC(0x31);
348 	seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
349 	tmp = RREG32_MC(0x32);
350 	seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
351 	tmp = RREG32_MC(0x33);
352 	seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
353 	tmp = RREG32_MC(0x34);
354 	seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
355 	tmp = RREG32_MC(0x35);
356 	seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
357 	tmp = RREG32_MC(0x36);
358 	seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
359 	tmp = RREG32_MC(0x37);
360 	seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);