drm2/radeon/radeon_legacy_encoders.c

642 	uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
661 	tmp = vclk_ecp_cntl &
663 	WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
665 	tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
666 	WREG32(RADEON_CRTC_EXT_CNTL, tmp);
668 	tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
672 		tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
674 		tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
677 		tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
679 		tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
681 		tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
683 	WREG32(RADEON_DAC_EXT_CNTL, tmp);
685 	tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
686 	tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
687 	WREG32(RADEON_DAC_CNTL, tmp);
689 	tmp = dac_macro_cntl;
690 	tmp &= ~(RADEON_DAC_PDWN_R |
694 	WREG32(RADEON_DAC_MACRO_CNTL, tmp);
784 	uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
789 	tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
790 	tmp &= 0xfffff;
793 		tmp ^= (1 << 22);
804 				tmp = tmds->tmds_pll[i].value ;
811 		if (tmp & 0xfff00000)
812 			tmds_pll_cntl = tmp;
815 			tmds_pll_cntl |= tmp;
818 		tmds_pll_cntl = tmp;
1307 	uint32_t disp_output_cntl, gpiopad_a, tmp;
1325 	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1326 	tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1327 	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1354 	tmp = RREG32(RADEON_TV_DAC_CNTL);
1355 	if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1358 	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1378 	uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1390 	tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1391 	WREG32(RADEON_DAC_CNTL2, tmp);
1393 	tmp = tv_master_cntl | RADEON_TV_ON;
1394 	tmp &= ~(RADEON_TV_ASYNC_RST |
1399 	tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1400 	WREG32(RADEON_TV_MASTER_CNTL, tmp);
1402 	tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1407 		tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1409 		tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1410 	WREG32(RADEON_TV_DAC_CNTL, tmp);
1412 	tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1417 	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1420 	tmp = RREG32(RADEON_TV_DAC_CNTL);
1421 	if (tmp & RADEON_TV_DAC_GDACDET) {
1424 	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1444 	uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
1465 	tmp = RREG32(RADEON_GPIO_MONID);
1466 	tmp &= ~RADEON_GPIO_A_0;
1467 	WREG32(RADEON_GPIO_MONID, tmp);
1494 		tmp = RREG32(RADEON_GPIO_MONID);
1495 		if (tmp & RADEON_GPIO_Y_0)
1533 	uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
1596 	tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1598 	WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1601 		tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
1602 		WREG32(RADEON_CRTC_EXT_CNTL, tmp);
1604 		tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1605 		tmp |= RADEON_CRTC2_CRT2_ON |
1607 		WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1611 			tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1612 			tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1613 			WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1615 			tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1616 			WREG32(RADEON_DISP_HW_DEBUG, tmp);
1620 	tmp = RADEON_TV_DAC_NBLANK |
1625 	WREG32(RADEON_TV_DAC_CNTL, tmp);
1627 	tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1631 		tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1633 		tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1636 		tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1638 		tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1640 	WREG32(RADEON_DAC_EXT_CNTL, tmp);
1642 	tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1643 	WREG32(RADEON_DAC_CNTL2, tmp);