drm2/radeon/r600_cs.c

372 	size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
452 	if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
464 				 radeon_bo_size(track->cb_color_bo[i]),
491 			    radeon_bo_size(track->cb_color_frag_bo[i])) {
496 					 radeon_bo_size(track->cb_color_frag_bo[i]));
509 		    radeon_bo_size(track->cb_color_tile_bo[i])) {
514 				 radeon_bo_size(track->cb_color_tile_bo[i]));
566 		tmp = radeon_bo_size(track->db_bo) - track->db_offset;
571 					radeon_bo_size(track->db_bo));
576 		size = radeon_bo_size(track->db_bo);
632 		if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
636 					radeon_bo_size(track->db_bo));
703 		if (size > radeon_bo_size(track->htile_bo)) {
705 				 __func__, __LINE__, radeon_bo_size(track->htile_bo),
732 					if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
735 							  radeon_bo_size(track->vgt_strmout_bo[i]));
1723 	if ((l0_size + word2) > radeon_bo_size(texture)) {
1727 			 l0_size, radeon_bo_size(texture));
1732 	if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1734 		  w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1934 			if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1936 					 (uintmax_t)tmp + size, radeon_bo_size(reloc->robj));
1964 			if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1966 					 (uintmax_t)tmp + size, radeon_bo_size(reloc->robj));
2128 				if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2131 						 size + offset, radeon_bo_size(reloc->robj));
2132 					ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
2240 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2242 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2273 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2275 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2292 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2294 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2321 		if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2323 				  (uintmax_t)offset + 8, radeon_bo_size(reloc->robj));
2346 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2348 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2370 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2372 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2647 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2649 					 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2714 			if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2716 					 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2719 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2721 					 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2737 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2739 					 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));