Lines Matching refs:tmp
152 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
157 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
168 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
169 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
327 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
331 tmp = RREG32(voltage->gpio.reg);
333 tmp |= voltage->gpio.mask;
335 tmp &= ~(voltage->gpio.mask);
336 WREG32(voltage->gpio.reg, tmp);
340 tmp = RREG32(voltage->gpio.reg);
342 tmp &= ~voltage->gpio.mask;
344 tmp |= voltage->gpio.mask;
345 WREG32(voltage->gpio.reg, tmp);
425 u32 tmp;
432 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
433 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
434 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
436 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
437 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
438 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
456 u32 tmp;
463 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
464 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
465 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
467 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
468 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
469 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
531 u32 tmp;
536 tmp = RREG32(RADEON_FP_GEN_CNTL);
538 tmp &= ~RADEON_FP_DETECT_INT_POL;
540 tmp |= RADEON_FP_DETECT_INT_POL;
541 WREG32(RADEON_FP_GEN_CNTL, tmp);
544 tmp = RREG32(RADEON_FP2_GEN_CNTL);
546 tmp &= ~RADEON_FP2_DETECT_INT_POL;
548 tmp |= RADEON_FP2_DETECT_INT_POL;
549 WREG32(RADEON_FP2_GEN_CNTL, tmp);
630 uint32_t tmp;
634 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
635 WREG32(RADEON_AIC_CNTL, tmp);
641 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
642 WREG32(RADEON_AIC_CNTL, tmp);
653 uint32_t tmp;
656 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
657 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
682 uint32_t tmp = 0;
690 tmp |= RADEON_SW_INT_ENABLE;
694 tmp |= RADEON_CRTC_VBLANK_MASK;
698 tmp |= RADEON_CRTC2_VBLANK_MASK;
701 tmp |= RADEON_FP_DETECT_MASK;
704 tmp |= RADEON_FP2_DETECT_MASK;
706 WREG32(RADEON_GEN_INT_CNTL, tmp);
712 u32 tmp;
717 tmp = RREG32(R_000044_GEN_INT_STATUS);
718 WREG32(R_000044_GEN_INT_STATUS, tmp);
920 u32 tmp;
923 tmp = RREG32(R_000E40_RBBM_STATUS);
924 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
1066 uint32_t tmp;
1116 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1120 tmp |= RADEON_BUF_SWAP_32BIT;
1122 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1128 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1141 tmp |= RADEON_RB_NO_UPDATE;
1145 WREG32(RADEON_CP_RB_CNTL, tmp);
1215 u32 tmp;
1228 tmp = value & 0x003fffff;
1229 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1243 tmp |= tile_flags;
1244 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1246 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1618 uint32_t tmp;
1690 tmp = idx_value & ~(0x7 << 2);
1691 tmp |= tile_flags;
1692 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1771 tmp = idx_value & ~(0x7 << 16);
1772 tmp |= tile_flags;
1773 ib[idx] = tmp;
1873 tmp = (idx_value >> 23) & 0x7;
1874 if (tmp == 2 || tmp == 6)
1876 tmp = (idx_value >> 27) & 0x7;
1877 if (tmp == 2 || tmp == 6)
1937 tmp = idx_value;
1940 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1941 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
2542 uint32_t tmp;
2545 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2546 if (tmp >= n) {
2557 uint32_t tmp;
2564 tmp = RREG32(RADEON_RBBM_STATUS);
2565 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2576 uint32_t tmp;
2580 tmp = RREG32(RADEON_MC_STATUS);
2581 if (tmp & RADEON_MC_IDLE) {
2606 uint32_t tmp;
2608 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2609 WREG32(RADEON_BUS_CNTL, tmp);
2614 u32 tmp;
2617 tmp = RREG32(R_000030_BUS_CNTL);
2618 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2620 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2622 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2623 tmp = RREG32(RADEON_BUS_CNTL);
2632 u32 status, tmp;
2644 tmp = RREG32(RADEON_CP_RB_CNTL);
2645 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2648 WREG32(RADEON_CP_RB_CNTL, tmp);
2689 u32 tmp;
2763 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2764 tmp &= ~RADEON_PM_MODE_SEL;
2765 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2774 uint32_t tmp;
2784 tmp = RREG32(RADEON_MEM_CNTL);
2785 if (tmp & RV100_HALF_MODE) {
2795 tmp = RREG32(RADEON_MEM_CNTL);
2796 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2943 uint32_t save, tmp;
2946 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2947 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2948 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
3041 uint32_t csq_stat, csq2_stat, tmp;
3068 tmp = RREG32(RADEON_CP_CSQ_DATA);
3069 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3074 tmp = RREG32(RADEON_CP_CSQ_DATA);
3075 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3080 tmp = RREG32(RADEON_CP_CSQ_DATA);
3081 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3091 uint32_t tmp;
3093 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3094 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3095 tmp = RREG32(RADEON_MC_FB_LOCATION);
3096 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3097 tmp = RREG32(RADEON_BUS_CNTL);
3098 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3099 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3100 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3101 tmp = RREG32(RADEON_AGP_BASE);
3102 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3103 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3104 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3105 tmp = RREG32(0x01D0);
3106 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3107 tmp = RREG32(RADEON_AIC_LO_ADDR);
3108 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3109 tmp = RREG32(RADEON_AIC_HI_ADDR);
3110 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3111 tmp = RREG32(0x01E4);
3112 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3701 uint32_t tmp = 0;
3721 tmp = RREG32(scratch);
3722 if (tmp == 0xDEADBEEF) {
3731 scratch, tmp);
3757 uint32_t tmp = 0;
3792 tmp = RREG32(scratch);
3793 if (tmp == 0xDEADBEEF) {
3802 scratch, tmp);
3872 u32 tmp;
3874 tmp = RREG8(R_0003C2_GENMO_WT);
3875 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3919 u32 tmp;
3924 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3925 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3927 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3928 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
4047 u32 tmp;
4049 tmp = RREG32(RADEON_CP_CSQ_CNTL);
4050 if (tmp) {
4053 tmp = RREG32(RADEON_CP_RB_CNTL);
4054 if (tmp) {
4057 tmp = RREG32(RADEON_SCRATCH_UMSK);
4058 if (tmp) {