Lines Matching defs:csr

1700 	u_int32_t csr = TULIP_CSR_READ(sc, csr_gp);
1701 if ((csr & (TULIP_GP_SMC_9332_OK10|TULIP_GP_SMC_9332_OK100)) == (TULIP_GP_SMC_9332_OK10|TULIP_GP_SMC_9332_OK100)) {
1704 } else if ((csr & TULIP_GP_SMC_9332_OK10) == 0) {
1802 u_int32_t csr = TULIP_CSR_READ(sc, csr_gp);
1803 if ((csr & (TULIP_GP_ZX34X_LNKFAIL|TULIP_GP_ZX34X_SYMDET|TULIP_GP_ZX34X_SIGDET)) == (TULIP_GP_ZX34X_LNKFAIL|TULIP_GP_ZX34X_SYMDET|TULIP_GP_ZX34X_SIGDET)) {
1806 } else if ((csr & TULIP_GP_ZX34X_LNKFAIL) == 0) {
1863 #define EMIT do { TULIP_CSR_WRITE(sc, csr_srom_mii, csr); DELAY(1); } while (0)
1868 unsigned bit, csr;
1870 csr = SROMSEL ; EMIT;
1871 csr = SROMSEL | SROMRD; EMIT;
1872 csr ^= SROMCS; EMIT;
1873 csr ^= SROMCLKON; EMIT;
1879 csr ^= SROMCLKOFF; EMIT; /* clock low; data not valid */
1880 csr ^= SROMCLKON; EMIT; /* clock high; data valid */
1882 csr ^= SROMCLKOFF; EMIT;
1883 csr ^= SROMCS; EMIT;
1884 csr = 0; EMIT;
1899 unsigned lastbit, data, bits, bit, csr;
1900 csr = SROMSEL ; EMIT;
1901 csr = SROMSEL | SROMRD; EMIT;
1902 csr ^= SROMCSON; EMIT;
1903 csr ^= SROMCLKON; EMIT;
1908 csr ^= SROMCLKOFF; EMIT; /* clock low; data not valid */
1910 csr ^= SROMDOUT; EMIT; /* clock low; invert data */
1914 csr ^= SROMCLKON; EMIT; /* clock high; data valid */
1917 csr ^= SROMCLKOFF; EMIT;
1921 csr ^= SROMCLKON; EMIT; /* clock high; data valid */
1923 csr ^= SROMCLKOFF; EMIT; /* clock low; data not valid */
1927 csr = SROMSEL | SROMRD; EMIT;
1928 csr = 0; EMIT;
1933 #define MII_EMIT do { TULIP_CSR_WRITE(sc, csr_srom_mii, csr); DELAY(1); } while (0)
1939 unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
1940 unsigned lastbit = (csr & MII_DOUT) ? msb : 0;
1943 csr |= MII_WR; MII_EMIT; /* clock low; assert write */
1948 csr ^= MII_DOUT; MII_EMIT; /* clock low; invert data */
1950 csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */
1952 csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */
1959 unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
1963 csr |= MII_DOUT; MII_EMIT; /* clock low; change data */
1964 csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */
1965 csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */
1966 csr ^= MII_DOUT; MII_EMIT; /* clock low; change data */
1968 csr |= MII_RD; MII_EMIT; /* clock low; switch to read */
1970 csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */
1971 csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */
1978 unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
1984 csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */
1987 csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */
1989 csr ^= MII_RD; MII_EMIT; /* clock low; turn off read */
1997 unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
2001 csr &= ~(MII_RD|MII_CLK); MII_EMIT;
2020 unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
2023 csr &= ~(MII_RD|MII_CLK); MII_EMIT;
2748 u_int32_t csr;
2758 while (((csr = TULIP_CSR_READ(sc, csr_enetrom)) & 0x80000000L) && cnt < 10000)
2760 sc->tulip_rombuf[idx] = csr & 0xFF;
3738 tulip_print_abnormal_interrupt(tulip_softc_t * const sc, u_int32_t csr)
3746 csr &= (1 << (sizeof(tulip_status_bits)/sizeof(tulip_status_bits[0]))) - 1;
3748 for (sep = " ", mask = 1; mask <= csr; mask <<= 1, msgp++) {
3749 if ((csr & mask) && *msgp != NULL) {
3770 u_int32_t csr;
3774 while ((csr = TULIP_CSR_READ(sc, csr_status)) & sc->tulip_intrmask) {
3775 TULIP_CSR_WRITE(sc, csr_status, csr);
3777 if (csr & TULIP_STS_SYSERROR) {
3778 sc->tulip_last_system_error = (csr & TULIP_STS_ERRORMASK) >> TULIP_STS_ERR_SHIFT;
3789 if (csr & (TULIP_STS_LINKPASS|TULIP_STS_LINKFAIL) & sc->tulip_intrmask) {
3794 (*sc->tulip_boardsw->bd_media_poll)(sc, csr & TULIP_STS_LINKFAIL
3797 csr &= ~TULIP_STS_ABNRMLINTR;
3801 if (csr & (TULIP_STS_RXINTR|TULIP_STS_RXNOBUF)) {
3803 if (csr & TULIP_STS_RXNOBUF)
3830 if (csr & TULIP_STS_ABNRMLINTR) {
3831 u_int32_t tmp = csr & sc->tulip_intrmask
3833 if (csr & TULIP_STS_TXUNDERFLOW) {