Lines Matching refs:adapter
41 * @adapter: the adapter performing the operation
54 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,
58 u32 val = t3_read_reg(adapter, reg);
74 * @adapter: the adapter to program
83 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n,
87 t3_write_reg(adapter, p->reg_addr + offset, p->val);
94 * @adapter: the adapter to program
102 void t3_set_reg_field(adapter_t *adapter, unsigned int addr, u32 mask, u32 val)
104 u32 v = t3_read_reg(adapter, addr) & ~mask;
106 t3_write_reg(adapter, addr, v | val);
107 (void) t3_read_reg(adapter, addr); /* flush */
112 * @adap: the adapter
150 adapter_t *adap = mc7->adapter;
207 int t3_i2c_read8(adapter_t *adapter, int chained, u8 *valp)
211 MDIO_LOCK(adapter);
212 t3_write_reg(adapter, A_I2C_OP,
214 ret = t3_wait_op_done_val(adapter, A_I2C_OP, F_I2C_BUSY, 0,
218 *valp = G_I2C_DATA(t3_read_reg(adapter, A_I2C_DATA));
220 MDIO_UNLOCK(adapter);
231 int t3_i2c_write8(adapter_t *adapter, int chained, u8 val)
235 MDIO_LOCK(adapter);
236 t3_write_reg(adapter, A_I2C_DATA, V_I2C_DATA(val));
237 t3_write_reg(adapter, A_I2C_OP,
239 ret = t3_wait_op_done_val(adapter, A_I2C_OP, F_I2C_BUSY, 0,
243 MDIO_UNLOCK(adapter);
263 int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr,
272 MDIO_LOCK(adapter);
273 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
274 t3_write_reg(adapter, A_MI1_ADDR, addr);
275 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
276 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
278 *valp = t3_read_reg(adapter, A_MI1_DATA);
279 MDIO_UNLOCK(adapter);
283 int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr,
292 MDIO_LOCK(adapter);
293 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
294 t3_write_reg(adapter, A_MI1_ADDR, addr);
295 t3_write_reg(adapter, A_MI1_DATA, val);
296 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
297 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
298 MDIO_UNLOCK(adapter);
310 static int mi1_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
316 MDIO_LOCK(adapter);
317 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0);
318 t3_write_reg(adapter, A_MI1_ADDR, addr);
319 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
320 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
321 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
323 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3));
324 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
327 *valp = t3_read_reg(adapter, A_MI1_DATA);
329 MDIO_UNLOCK(adapter);
333 static int mi1_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
339 MDIO_LOCK(adapter);
340 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0);
341 t3_write_reg(adapter, A_MI1_ADDR, addr);
342 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
343 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
344 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
346 t3_write_reg(adapter, A_MI1_DATA, val);
347 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
348 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
351 MDIO_UNLOCK(adapter);
648 * @adapter: adapter to read
657 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data)
661 unsigned int base = adapter->params.pci.vpd_cap_addr;
666 t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR, (u16)addr);
669 t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val);
673 CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr);
676 t3_os_pci_read_config_4(adapter, base + PCI_VPD_DATA, data);
683 * @adapter: adapter to write
690 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data)
694 unsigned int base = adapter->params.pci.vpd_cap_addr;
699 t3_os_pci_write_config_4(adapter, base + PCI_VPD_DATA,
701 t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR,
705 t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val);
709 CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr);
717 * @adapter: the adapter
722 int t3_seeprom_wp(adapter_t *adapter, int enable)
724 return t3_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
737 * @adapter: the adapter
743 static int get_desc_len(adapter_t *adapter, u32 offset)
752 ret = t3_seeprom_read(adapter, read_offset, &tmp);
760 ret = t3_seeprom_read(adapter, read_offset + 4, &tmp);
775 * @adapter: the adapter
780 static int is_end_tag(adapter_t * adapter, u32 offset)
788 ret = t3_seeprom_read(adapter, read_offset, &tmp);
801 * @adapter: the adapter
807 int t3_get_vpd_len(adapter_t * adapter, struct generic_vpd *vpd)
815 ret = is_end_tag(adapter, offset);
821 inc = get_desc_len(adapter, offset);
832 * @adapter: the adapter
839 int t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd)
844 ret = t3_seeprom_read(adapter, vpd->offset + i,
856 * @adapter: adapter to read
861 static int get_vpd_params(adapter_t *adapter, struct vpd_params *p)
870 ret = t3_seeprom_read(adapter, VPD_BASE, (u32 *)&vpd);
876 ret = t3_seeprom_read(adapter, addr + i,
891 if (adapter->params.rev == 0 && !vpd.port0_data[0]) {
892 p->port_type[0] = uses_xaui(adapter) ? 1 : 2;
893 p->port_type[1] = uses_xaui(adapter) ? 6 : 2;
948 * @adapter: the adapter
957 static int sf1_read(adapter_t *adapter, unsigned int byte_cnt, int cont,
964 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
966 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
967 ret = t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
969 *valp = t3_read_reg(adapter, A_SF_DATA);
975 * @adapter: the adapter
984 static int sf1_write(adapter_t *adapter, unsigned int byte_cnt, int cont,
989 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
991 t3_write_reg(adapter, A_SF_DATA, val);
992 t3_write_reg(adapter, A_SF_OP,
994 return t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
999 * @adapter: the adapter
1005 static int flash_wait_op(adapter_t *adapter, int attempts, int delay)
1011 if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 ||
1012 (ret = sf1_read(adapter, 1, 0, &status)) != 0)
1025 * @adapter: the adapter
1036 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
1046 if ((ret = sf1_write(adapter, 4, 1, addr)) != 0 ||
1047 (ret = sf1_read(adapter, 1, 1, data)) != 0)
1051 ret = sf1_read(adapter, 4, nwords > 1, data);
1062 * @adapter: the adapter
1074 static int t3_write_flash(adapter_t *adapter, unsigned int addr,
1087 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
1088 (ret = sf1_write(adapter, 4, 1, val)) != 0)
1098 ret = sf1_write(adapter, c, c != left, val);
1102 if ((ret = flash_wait_op(adapter, 5, 1)) != 0)
1106 ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
1118 * @adapter: the adapter
1123 int t3_get_tp_version(adapter_t *adapter, u32 *vers)
1128 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
1129 ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0,
1134 *vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
1141 * @adapter: the adapter
1144 int t3_check_tpsram_version(adapter_t *adapter)
1150 if (adapter->params.rev == T3_REV_A)
1154 ret = t3_get_tp_version(adapter, &vers);
1158 vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
1166 CH_ERR(adapter, "found wrong TP version (%u.%u), "
1176 * @adapter: the adapter
1180 * Checks if an adapter's tp sram is compatible with the driver.
1183 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_sram, unsigned int size)
1193 CH_ERR(adapter, "corrupted protocol SRAM image, checksum %u\n",
1208 * @adapter: the adapter
1215 int t3_get_fw_version(adapter_t *adapter, u32 *vers)
1217 int ret = t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0);
1221 return t3_read_flash(adapter, FW_VERS_ADDR_PRE8, 1, vers, 0);
1226 * @adapter: the adapter
1228 * Checks if an adapter's FW is compatible with the driver. Returns 0
1231 int t3_check_fw_version(adapter_t *adapter)
1237 ret = t3_get_fw_version(adapter, &vers);
1250 CH_WARN(adapter, "found old FW minor version(%u.%u), "
1254 CH_WARN(adapter, "found newer FW version(%u.%u), "
1264 * @adapter: the adapter
1270 static int t3_flash_erase_sectors(adapter_t *adapter, int start, int end)
1275 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
1276 (ret = sf1_write(adapter, 4, 0,
1278 (ret = flash_wait_op(adapter, 5, 500)) != 0)
1287 * @adapter: the adapter
1296 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size)
1321 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1326 ret = t3_flash_erase_sectors(adapter, fw_sector, fw_sector);
1334 ret = t3_write_flash(adapter, addr, chunk_size, fw_data, 1);
1343 ret = t3_write_flash(adapter, fw_version_addr, 4, fw_data, 1);
1346 CH_ERR(adapter, "firmware download failed, error %d\n", ret);
1352 * @adapter: the adapter
1360 int t3_load_boot(adapter_t *adapter, u8 *boot_data, unsigned int size)
1374 CH_ERR(adapter, "boot image too small/large\n");
1378 CH_ERR(adapter, "boot image missing signature\n");
1382 CH_ERR(adapter, "boot image header length != image length\n");
1386 ret = t3_flash_erase_sectors(adapter, boot_sector, boot_end);
1393 ret = t3_write_flash(adapter, addr, chunk_size, boot_data, 0);
1404 CH_ERR(adapter, "boot image download failed, error %d\n", ret);
1412 * @adap: the adapter
1444 *rx_cfg = t3_read_reg(mac->adapter, A_XGM_RX_CFG + mac->offset);
1445 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG + mac->offset,
1449 *rx_hash_high = t3_read_reg(mac->adapter, A_XGM_RX_HASH_HIGH +
1451 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH + mac->offset, 0);
1453 *rx_hash_low = t3_read_reg(mac->adapter, A_XGM_RX_HASH_LOW +
1455 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW + mac->offset, 0);
1465 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG + mac->offset,
1468 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH + mac->offset,
1470 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW + mac->offset,
1474 static int t3_detect_link_fault(adapter_t *adapter, int port_id)
1476 struct port_info *pi = adap2pinfo(adapter, port_id);
1483 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0);
1486 (void) t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset);
1487 t3_xgm_intr_enable(adapter, port_id);
1490 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, F_RXEN);
1493 link_fault = t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset);
1497 static void t3_clear_faults(adapter_t *adapter, int port_id)
1499 struct port_info *pi = adap2pinfo(adapter, port_id);
1502 if (adapter->params.nports <= 2) {
1503 t3_xgm_intr_disable(adapter, pi->port_id);
1504 t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset);
1505 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, F_XGM_INT);
1506 t3_set_reg_field(adapter, A_XGM_INT_ENABLE + mac->offset,
1508 t3_xgm_intr_enable(adapter, pi->port_id);
1514 * @adapter: the adapter
1521 void t3_link_changed(adapter_t *adapter, int port_id)
1524 struct port_info *pi = adap2pinfo(adapter, port_id);
1555 if (adapter->params.nports <= 2 &&
1558 link_fault = t3_detect_link_fault(adapter, port_id);
1565 if (uses_xaui(adapter)) {
1566 if (adapter->params.rev >= T3_REV_C)
1578 t3_clear_faults(adapter, port_id);
1597 if (adapter->params.rev > 0 && uses_xaui(adapter)) {
1599 if (adapter->params.rev >= T3_REV_C)
1604 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1609 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + mac->offset,
1613 t3_set_reg_field(adapter, A_XGM_STAT_CTRL + mac->offset,
1615 t3_clear_faults(adapter, port_id);
1621 if (adapter->params.rev > 0 && uses_xaui(adapter)) {
1622 t3_write_reg(adapter,
1626 t3_xgm_intr_disable(adapter, pi->port_id);
1627 if (adapter->params.nports <= 2) {
1628 t3_set_reg_field(adapter,
1638 t3_set_reg_field(adapter,
1640 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0);
1641 t3_write_reg(adapter,
1643 t3_write_reg(adapter,
1648 t3_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc,
1690 if (!is_10G(phy->adapter))
1704 * @adapter: the adapter
1705 * @ports: bitmap of adapter ports to operate on
1710 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on)
1712 t3_set_reg_field(adapter, A_TP_OUT_CONFIG,
1726 * @adapter: the adapter that generated the interrupt
1739 static int t3_handle_intr_status(adapter_t *adapter, unsigned int reg,
1745 unsigned int status = t3_read_reg(adapter, reg) & mask;
1751 CH_ALERT(adapter, "%s (0x%x)\n",
1755 CH_WARN(adapter, "%s (0x%x)\n",
1761 t3_write_reg(adapter, reg, status);
1823 static void pci_intr_handler(adapter_t *adapter)
1851 if (t3_handle_intr_status(adapter, A_PCIX_INT_CAUSE, PCIX_INTR_MASK,
1852 pcix1_intr_info, adapter->irq_stats))
1853 t3_fatal_err(adapter);
1859 static void pcie_intr_handler(adapter_t *adapter)
1881 if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR)
1882 CH_ALERT(adapter, "PEX error code 0x%x\n",
1883 t3_read_reg(adapter, A_PCIE_PEX_ERR));
1885 if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK,
1886 pcie_intr_info, adapter->irq_stats))
1887 t3_fatal_err(adapter);
1893 static void tp_intr_handler(adapter_t *adapter)
1908 if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff,
1909 adapter->params.rev < T3_REV_C ?
1911 t3_fatal_err(adapter);
1917 static void cim_intr_handler(adapter_t *adapter)
1947 if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, CIM_INTR_MASK,
1949 t3_fatal_err(adapter);
1955 static void ulprx_intr_handler(adapter_t *adapter)
1969 if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff,
1971 t3_fatal_err(adapter);
1977 static void ulptx_intr_handler(adapter_t *adapter)
1988 if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff,
1989 ulptx_intr_info, adapter->irq_stats))
1990 t3_fatal_err(adapter);
2005 static void pmtx_intr_handler(adapter_t *adapter)
2018 if (t3_handle_intr_status(adapter, A_PM1_TX_INT_CAUSE, 0xffffffff,
2020 t3_fatal_err(adapter);
2035 static void pmrx_intr_handler(adapter_t *adapter)
2048 if (t3_handle_intr_status(adapter, A_PM1_RX_INT_CAUSE, 0xffffffff,
2050 t3_fatal_err(adapter);
2056 static void cplsw_intr_handler(adapter_t *adapter)
2068 if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff,
2070 t3_fatal_err(adapter);
2076 static void mps_intr_handler(adapter_t *adapter)
2083 if (t3_handle_intr_status(adapter, A_MPS_INT_CAUSE, 0xffffffff,
2085 t3_fatal_err(adapter);
2095 adapter_t *adapter = mc7->adapter;
2096 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);
2100 CH_WARN(adapter, "%s MC7 correctable error at addr 0x%x, "
2102 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR),
2103 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0),
2104 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1),
2105 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2));
2110 CH_ALERT(adapter, "%s MC7 uncorrectable error at addr 0x%x, "
2112 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR),
2113 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0),
2114 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1),
2115 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2));
2120 CH_ALERT(adapter, "%s MC7 parity error 0x%x\n",
2127 if (adapter->params.rev > 0)
2128 addr = t3_read_reg(adapter,
2131 CH_ALERT(adapter, "%s MC7 address error: 0x%x\n",
2136 t3_fatal_err(adapter);
2138 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause);
2203 static int phy_intr_handler(adapter_t *adapter)
2205 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
2207 for_each_port(adapter, i) {
2208 struct port_info *p = adap2pinfo(adapter, i);
2213 if (cause & (1 << adapter_info(adapter)->gpio_intr[i])) {
2221 t3_os_phymod_changed(adapter, i);
2223 CH_WARN(adapter, "Operation affected due to "
2229 t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause);
2235 * @adapter: the adapter
2241 int t3_slow_intr_handler(adapter_t *adapter)
2243 u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0);
2245 cause &= adapter->slow_intr_mask;
2249 if (is_pcie(adapter))
2250 pcie_intr_handler(adapter);
2252 pci_intr_handler(adapter);
2255 t3_sge_err_intr_handler(adapter);
2257 mc7_intr_handler(&adapter->pmrx);
2259 mc7_intr_handler(&adapter->pmtx);
2261 mc7_intr_handler(&adapter->cm);
2263 cim_intr_handler(adapter);
2265 tp_intr_handler(adapter);
2267 ulprx_intr_handler(adapter);
2269 ulptx_intr_handler(adapter);
2271 pmrx_intr_handler(adapter);
2273 pmtx_intr_handler(adapter);
2275 cplsw_intr_handler(adapter);
2277 mps_intr_handler(adapter);
2279 t3_mc5_intr_handler(&adapter->mc5);
2281 mac_intr_handler(adapter, 0);
2283 mac_intr_handler(adapter, 1);
2285 phy_intr_handler(adapter);
2288 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause);
2289 (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
2306 * @adapter: the adapter whose interrupts should be enabled
2312 void t3_intr_enable(adapter_t *adapter)
2328 adapter->slow_intr_mask = PL_INTR_MASK;
2330 t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0);
2331 t3_write_reg(adapter, A_TP_INT_ENABLE,
2332 adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff);
2333 t3_write_reg(adapter, A_SG_INT_ENABLE, SGE_INTR_MASK);
2335 if (adapter->params.rev > 0) {
2336 t3_write_reg(adapter, A_CPL_INTR_ENABLE,
2338 t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
2342 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK);
2343 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
2346 t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter));
2348 if (is_pcie(adapter))
2349 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
2351 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK);
2352 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask);
2353 (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
2358 * @adapter: the adapter whose interrupts should be disabled
2363 void t3_intr_disable(adapter_t *adapter)
2365 t3_write_reg(adapter, A_PL_INT_ENABLE0, 0);
2366 (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
2367 adapter->slow_intr_mask = 0;
2372 * @adapter: the adapter whose interrupts should be cleared
2376 void t3_intr_clear(adapter_t *adapter)
2399 for_each_port(adapter, i)
2400 t3_port_intr_clear(adapter, i);
2403 t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff);
2405 if (is_pcie(adapter))
2406 t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff);
2407 t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff);
2408 (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
2411 void t3_xgm_intr_enable(adapter_t *adapter, int idx)
2413 struct port_info *pi = adap2pinfo(adapter, idx);
2415 t3_write_reg(adapter, A_XGM_XGM_INT_ENABLE + pi->mac.offset,
2419 void t3_xgm_intr_disable(adapter_t *adapter, int idx)
2421 struct port_info *pi = adap2pinfo(adapter, idx);
2423 t3_write_reg(adapter, A_XGM_XGM_INT_DISABLE + pi->mac.offset,
2429 * @adapter: associated adapter
2433 * adapter port.
2435 void t3_port_intr_enable(adapter_t *adapter, int idx)
2437 struct port_info *pi = adap2pinfo(adapter, idx);
2439 t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, XGM_INTR_MASK);
2445 * @adapter: associated adapter
2449 * adapter port.
2451 void t3_port_intr_disable(adapter_t *adapter, int idx)
2453 struct port_info *pi = adap2pinfo(adapter, idx);
2455 t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, 0);
2461 * @adapter: associated adapter
2465 * adapter port.
2467 void t3_port_intr_clear(adapter_t *adapter, int idx)
2469 struct port_info *pi = adap2pinfo(adapter, idx);
2471 t3_write_reg(adapter, A_XGM_INT_CAUSE + pi->mac.offset, 0xffffffff);
2479 * @adapter: the adapter
2486 static int t3_sge_write_context(adapter_t *adapter, unsigned int id,
2496 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
2497 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
2498 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0x17ffffff);
2499 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
2501 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
2502 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
2503 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff);
2504 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
2506 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2508 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2514 * @adapter: the adapter
2541 * @adapter: the adapter to configure
2556 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable,
2565 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2569 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) |
2571 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) |
2574 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, (u32)base_addr);
2576 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
2580 return t3_sge_write_context(adapter, id, F_EGRESS);
2585 * @adapter: the adapter to configure
2599 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable,
2605 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2609 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, (u32)base_addr);
2611 t3_write_reg(adapter, A_SG_CONTEXT_DATA1,
2614 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) |
2617 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
2620 return t3_sge_write_context(adapter, id, F_FREELIST);
2625 * @adapter: the adapter to configure
2638 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
2646 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2650 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) |
2652 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr);
2654 ctrl = t3_read_reg(adapter, A_SG_CONTROL);
2660 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2662 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres);
2663 return t3_sge_write_context(adapter, id, F_RESPONSEQ);
2668 * @adapter: the adapter to configure
2681 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr,
2687 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2691 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size));
2692 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr);
2694 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2698 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) |
2700 return t3_sge_write_context(adapter, id, F_CQ);
2705 * @adapter: the adapter
2712 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable)
2714 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2717 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2718 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2719 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2720 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID);
2721 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable));
2722 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2724 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2730 * @adapter: the adapter
2736 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id)
2738 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2741 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2742 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2743 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE));
2744 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2745 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0);
2746 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2748 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2754 * @adapter: the adapter
2760 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id)
2762 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2765 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2766 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2767 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2768 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2769 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2770 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2772 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2778 * @adapter: the adapter
2784 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id)
2786 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2789 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2790 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2791 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2792 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2793 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2794 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2796 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2802 * @adapter: the adapter
2814 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
2819 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2822 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16);
2823 t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) |
2825 if (t3_wait_op_done_val(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2830 if (adapter->params.rev > 0)
2833 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2835 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD,
2839 return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0));
2847 * @adapter: the adapter
2854 static int t3_sge_read_context(unsigned int type, adapter_t *adapter,
2857 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2860 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2862 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0,
2865 data[0] = t3_read_reg(adapter, A_SG_CONTEXT_DATA0);
2866 data[1] = t3_read_reg(adapter, A_SG_CONTEXT_DATA1);
2867 data[2] = t3_read_reg(adapter, A_SG_CONTEXT_DATA2);
2868 data[3] = t3_read_reg(adapter, A_SG_CONTEXT_DATA3);
2874 * @adapter: the adapter
2881 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4])
2885 return t3_sge_read_context(F_EGRESS, adapter, id, data);
2890 * @adapter: the adapter
2897 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4])
2901 return t3_sge_read_context(F_CQ, adapter, id, data);
2906 * @adapter: the adapter
2913 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4])
2917 return t3_sge_read_context(F_FREELIST, adapter, id, data);
2922 * @adapter: the adapter
2929 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4])
2933 return t3_sge_read_context(F_RESPONSEQ, adapter, id, data);
2938 * @adapter: the adapter
2948 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
2962 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val);
2967 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2973 t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config);
2978 * @adapter: the adapter
2984 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map)
2991 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE,
2993 val = t3_read_reg(adapter, A_TP_RSS_LKP_TABLE);
3002 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
3004 val = t3_read_reg(adapter, A_TP_RSS_MAP_TABLE);
3014 * @adap: the adapter
3028 * @adap: the adapter
3045 * @adap: the adapter
3059 * @adap: the adapter
3095 * @adap: the adapter
3243 * @adap: the adapter to set
3288 * @adap: the adapter
3318 * @adap: the adapter
3404 * @adap: the adapter
3448 * @adap: the adapter
3468 * @adap: the adapter
3490 * @adap: the adapter
3503 * @adap: the adapter
3520 * @adap: the adapter
3565 * @adapter: the adapter
3591 * @adapter: the adapter
3599 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
3620 tp_wr_indirect(adapter, addr++, key[0]);
3621 tp_wr_indirect(adapter, addr++, mask[0]);
3622 tp_wr_indirect(adapter, addr++, key[1]);
3623 tp_wr_indirect(adapter, addr++, mask[1]);
3624 tp_wr_indirect(adapter, addr++, key[2]);
3625 tp_wr_indirect(adapter, addr++, mask[2]);
3626 tp_wr_indirect(adapter, addr++, key[3]);
3627 tp_wr_indirect(adapter, addr, mask[3]);
3628 (void) t3_read_reg(adapter, A_TP_PIO_DATA);
3633 * @adapter: the adapter
3641 void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp,
3647 key[0] = tp_rd_indirect(adapter, addr++);
3648 mask[0] = tp_rd_indirect(adapter, addr++);
3649 key[1] = tp_rd_indirect(adapter, addr++);
3650 mask[1] = tp_rd_indirect(adapter, addr++);
3651 key[2] = tp_rd_indirect(adapter, addr++);
3652 mask[2] = tp_rd_indirect(adapter, addr++);
3653 key[3] = tp_rd_indirect(adapter, addr++);
3654 mask[3] = tp_rd_indirect(adapter, addr);
3678 * @adap: the adapter
3722 * @adap: the adapter
3751 * @adap: the adapter
3791 * @adap: the adapter
3819 * @adap: the adapter
3835 * @adap: the adapter
3878 static int calibrate_xgm(adapter_t *adapter)
3880 if (uses_xaui(adapter)) {
3884 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0);
3885 (void) t3_read_reg(adapter, A_XGM_XAUI_IMP);
3887 v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
3889 t3_write_reg(adapter, A_XGM_XAUI_IMP,
3894 CH_ERR(adapter, "MAC calibration failed\n");
3897 t3_write_reg(adapter, A_XGM_RGMII_IMP,
3899 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
3905 static void calibrate_xgm_t3b(adapter_t *adapter)
3907 if (!uses_xaui(adapter)) {
3908 t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET |
3910 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALRESET, 0);
3911 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0,
3913 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
3915 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALUPDATE, 0);
3916 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_CALUPDATE);
3935 static int wrreg_wait(adapter_t *adapter, unsigned int addr, u32 val)
3937 t3_write_reg(adapter, addr, val);
3938 (void) t3_read_reg(adapter, addr); /* flush */
3939 if (!(t3_read_reg(adapter, addr) & F_BUSY))
3941 CH_ERR(adapter, "write to MC7 register 0x%x timed out\n", addr);
3960 adapter_t *adapter = mc7->adapter;
3966 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3971 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
3972 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3976 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
3977 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
3979 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
3981 CH_ERR(adapter, "%s MC7 calibration timed out\n",
3987 t3_write_reg(adapter, mc7->offset + A_MC7_PARM,
3993 t3_write_reg(adapter, mc7->offset + A_MC7_CFG,
3995 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3998 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB,
4003 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
4004 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) ||
4005 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) ||
4006 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
4010 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100);
4011 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL,
4016 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
4017 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
4018 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
4019 wrreg_wait(adapter, mc7->offset + A_MC7_MODE,
4021 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) ||
4022 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
4029 t3_write_reg(adapter, mc7->offset + A_MC7_REF,
4031 (void) t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */
4033 t3_write_reg(adapter, mc7->offset + A_MC7_ECC,
4035 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0);
4036 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);
4037 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,
4039 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));
4040 (void) t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */
4045 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
4048 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name);
4053 t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY);
4085 * Gen2 adapter pcie bridge compatibility requires minimum
4128 * @adapter: the adapter
4139 int t3_init_hw(adapter_t *adapter, u32 fw_params)
4142 const struct vpd_params *vpd = &adapter->params.vpd;
4144 if (adapter->params.rev > 0)
4145 calibrate_xgm_t3b(adapter);
4146 else if (calibrate_xgm(adapter))
4149 if (adapter->params.nports > 2)
4150 t3_mac_init(&adap2pinfo(adapter, 0)->mac);
4153 partition_mem(adapter, &adapter->params.tp);
4155 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) ||
4156 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) ||
4157 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) ||
4158 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers,
4159 adapter->params.mc5.nfilters,
4160 adapter->params.mc5.nroutes))
4164 if (clear_sge_ctxt(adapter, i, F_CQ))
4168 if (tp_init(adapter, &adapter->params.tp))
4171 t3_tp_set_coalescing_size(adapter,
4172 min(adapter->params.sge.max_pkt_size,
4174 t3_tp_set_max_rxsize(adapter,
4175 min(adapter->params.sge.max_pkt_size, 16384U));
4176 ulp_config(adapter, &adapter->params.tp);
4177 if (is_pcie(adapter))
4178 config_pcie(adapter);
4180 t3_set_reg_field(adapter, A_PCIX_CFG, 0,
4183 if (adapter->params.rev == T3_REV_C)
4184 t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0,
4187 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
4188 t3_write_reg(adapter, A_PM1_RX_MODE, 0);
4189 t3_write_reg(adapter, A_PM1_TX_MODE, 0);
4190 chan_init_hw(adapter, adapter->params.chan_map);
4191 t3_sge_init(adapter, &adapter->params.sge);
4192 t3_set_reg_field(adapter, A_PL_RST, 0, F_FATALPERREN);
4194 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter));
4196 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
4197 t3_write_reg(adapter, A_CIM_BOOT_CFG,
4199 (void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
4204 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
4206 CH_ERR(adapter, "uP initialization timed out\n");
4217 * @adapter: the adapter
4223 static void __devinit get_pci_mode(adapter_t *adapter, struct pci_params *p)
4228 pcie_cap = t3_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4234 t3_os_pci_read_config_2(adapter, pcie_cap + PCI_EXP_LNKSTA,
4240 pci_mode = t3_read_reg(adapter, A_PCIX_MODE);
4298 static void __devinit mc7_prep(adapter_t *adapter, struct mc7 *mc7,
4303 mc7->adapter = adapter;
4306 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
4311 void mac_prep(struct cmac *mac, adapter_t *adapter, int index)
4315 mac->adapter = adapter;
4316 mac->multiport = adapter->params.nports > 2;
4323 /* Gen2 adapter uses VPD xauicfg[] to notify driver which MAC
4326 t3_os_pci_read_config_2(adapter, 0x2, &devid);
4329 (!adapter->params.vpd.xauicfg[1] && (devid==0x37)))
4334 if (adapter->params.rev == 0 && uses_xaui(adapter)) {
4335 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset,
4336 is_10G(adapter) ? 0x2901c04 : 0x2301c04);
4337 t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset,
4344 * @adapter: the adapter
4345 * @ai: contains information about the adapter type and properties
4351 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai)
4353 u32 val = V_PORTSPEED(is_10G(adapter) || adapter->params.nports > 2 ?
4357 mi1_init(adapter, ai);
4358 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */
4359 V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1));
4360 t3_write_reg(adapter, A_T3DBG_GPIO_EN,
4362 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0);
4363 t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff));
4365 if (adapter->params.rev == 0 || !uses_xaui(adapter))
4369 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
4370 (void) t3_read_reg(adapter, A_XGM_PORT_CFG);
4373 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
4374 (void) t3_read_reg(adapter, A_XGM_PORT_CFG);
4375 t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val);
4376 (void) t3_read_reg(adapter, A_XGM_PORT_CFG);
4380 * t3_reset_adapter - reset the adapter
4381 * @adapter: the adapter
4383 * Reset the adapter.
4385 int t3_reset_adapter(adapter_t *adapter)
4388 adapter->params.rev < T3_REV_B2 && is_pcie(adapter);
4392 t3_os_pci_save_state(adapter);
4393 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE);
4401 t3_os_pci_read_config_2(adapter, 0x00, &devid);
4410 t3_os_pci_restore_state(adapter);
4446 * @adapter: the adapter
4447 * @ai: contains information about the adapter type and properties
4449 * Initialize adapter SW state for the various HW modules, set initial
4450 * values for some adapter tunables, take PHYs out of reset, and
4453 int __devinit t3_prep_adapter(adapter_t *adapter,
4459 get_pci_mode(adapter, &adapter->params.pci);
4461 adapter->params.info = ai;
4462 adapter->params.nports = ai->nports0 + ai->nports1;
4463 adapter->params.chan_map = (!!ai->nports0) | (!!ai->nports1 << 1);
4464 adapter->params.rev = t3_read_reg(adapter, A_PL_REV);
4467 * We used to only run the "adapter check task" once a second if
4472 * adapter state once a second ...
4474 adapter->params.linkpoll_period = 10;
4476 if (adapter->params.nports > 2)
4477 adapter->params.stats_update_period = VSC_STATS_ACCUM_SECS;
4479 adapter->params.stats_update_period = is_10G(adapter) ?
4481 adapter->params.pci.vpd_cap_addr =
4482 t3_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4484 ret = get_vpd_params(adapter, &adapter->params.vpd);
4488 if (reset && t3_reset_adapter(adapter))
4491 if (adapter->params.vpd.mclk) {
4492 struct tp_params *p = &adapter->params.tp;
4494 mc7_prep(adapter, &adapter->pmrx, MC7_PMRX_BASE_ADDR, "PMRX");
4495 mc7_prep(adapter, &adapter->pmtx, MC7_PMTX_BASE_ADDR, "PMTX");
4496 mc7_prep(adapter, &adapter->cm, MC7_CM_BASE_ADDR, "CM");
4498 p->nchan = adapter->params.chan_map == 3 ? 2 : 1;
4499 p->pmrx_size = t3_mc7_size(&adapter->pmrx);
4500 p->pmtx_size = t3_mc7_size(&adapter->pmtx);
4501 p->cm_size = t3_mc7_size(&adapter->cm);
4505 p->tx_pg_size = is_10G(adapter) ? 64 * 1024 : 16 * 1024;
4509 adapter->params.rev > 0 ? 12 : 6;
4510 p->tre = fls(adapter->params.vpd.cclk / (1000 / TP_TMR_RES)) -
4512 p->dack_re = fls(adapter->params.vpd.cclk / 10) - 1; /* 100us */
4515 adapter->params.offload = t3_mc7_size(&adapter->pmrx) &&
4516 t3_mc7_size(&adapter->pmtx) &&
4517 t3_mc7_size(&adapter->cm);
4519 t3_sge_prep(adapter, &adapter->params.sge);
4521 if (is_offload(adapter)) {
4522 adapter->params.mc5.nservers = DEFAULT_NSERVERS;
4524 adapter->params.mc5.nfilters = 0;
4525 adapter->params.mc5.nroutes = 0;
4526 t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT);
4528 init_mtus(adapter->params.mtus);
4529 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4532 early_hw_init(adapter, ai);
4533 ret = init_parity(adapter);
4537 if (adapter->params.nports > 2 &&
4538 (ret = t3_vsc7323_init(adapter, adapter->params.nports)))
4541 for_each_port(adapter, i) {
4544 struct port_info *p = adap2pinfo(adapter, i);
4547 unsigned port_type = adapter->params.vpd.port_type[j];
4556 if (j >= ARRAY_SIZE(adapter->params.vpd.port_type))
4563 mac_prep(&p->mac, adapter, j);
4571 memcpy(hw_addr, adapter->params.vpd.eth_base, 5);
4572 hw_addr[5] = adapter->params.vpd.eth_base[5] + i;
4574 t3_os_set_hw_addr(adapter, i, hw_addr);
4580 * changes, schedule a scan of the adapter links at least
4584 adapter->params.linkpoll_period > 10)
4585 adapter->params.linkpoll_period = 10;
4593 * @adapter: the adapter
4639 void t3_led_ready(adapter_t *adapter)
4641 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
4645 void t3_port_failover(adapter_t *adapter, int port)
4650 t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE,
4654 void t3_failover_done(adapter_t *adapter, int port)
4656 t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE,
4660 void t3_failover_clear(adapter_t *adapter)
4662 t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE,
4666 static int t3_cim_hac_read(adapter_t *adapter, u32 addr, u32 *val)
4670 t3_write_reg(adapter, A_CIM_HOST_ACC_CTRL, addr);
4671 if (t3_wait_op_done_val(adapter, A_CIM_HOST_ACC_CTRL,
4675 *val = t3_read_reg(adapter, A_CIM_HOST_ACC_DATA);
4680 static int t3_cim_hac_write(adapter_t *adapter, u32 addr, u32 val)
4684 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, val);
4687 t3_write_reg(adapter, A_CIM_HOST_ACC_CTRL, addr);
4689 if (t3_wait_op_done_val(adapter, A_CIM_HOST_ACC_CTRL,
4695 int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index,
4704 ret = t3_cim_hac_read(adapter, LA_CTRL, &v);
4712 ret = t3_cim_hac_write(adapter, LA_CTRL, 0);
4719 ret = t3_cim_hac_write(adapter, LA_CTRL, v);
4723 ret = t3_cim_hac_read(adapter, LA_CTRL, &v);
4731 ret = t3_cim_hac_read(adapter, LA_CTRL, &v);
4739 ret = t3_cim_hac_read(adapter, LA_DATA, &v);
4746 ret = t3_cim_hac_read(adapter, LA_CTRL, &v);
4754 t3_cim_hac_write(adapter, LA_CTRL, 1);
4758 int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data)
4767 ret = t3_cim_hac_read(adapter, (4 * i), &v);
4778 ret = t3_cim_hac_read(adapter, base_addr + 4 * j, &v);