Lines Matching refs:BWN_PHY_OFDM
381 #define BWN_PHY_OFDM(reg) ((reg) | BWN_PHYROUTE_OFDM_GPHY)
384 #define BWN_PHY_VERSION_OFDM BWN_PHY_OFDM(0x00)
385 #define BWN_PHY_BBANDCFG BWN_PHY_OFDM(0x01)
388 #define BWN_PHY_PWRDOWN BWN_PHY_OFDM(0x03)
389 #define BWN_PHY_CRSTHRES1_R1 BWN_PHY_OFDM(0x06)
390 #define BWN_PHY_CRSGAIN_CTL BWN_PHY_OFDM(0x10)
391 #define BWN_PHY_MINPWR_LEVEL BWN_PHY_OFDM(0x16)
392 #define BWN_PHY_OFDMSYNCTHRESH0 BWN_PHY_OFDM(0x17)
393 #define BWN_PHY_IDLEAFTERPKTRXTO BWN_PHY_OFDM(0x1a)
394 #define BWN_PHY_LNAHPFCTL BWN_PHY_OFDM(0x1c)
395 #define BWN_PHY_DCOFFSETTRANSIENT BWN_PHY_OFDM(0x1c) /* for LP */
396 #define BWN_PHY_PREAMBLECONFIRMTO BWN_PHY_OFDM(0x1e)
397 #define BWN_PHY_CLIPTHRESH BWN_PHY_OFDM(0x1f)
398 #define BWN_PHY_LPFGAINCTL BWN_PHY_OFDM(0x20)
399 #define BWN_PHY_CLIPCTRTHRESH BWN_PHY_OFDM(0x20) /* for LP */
400 #define BWN_PHY_HIGAINDB BWN_PHY_OFDM(0x23)
401 #define BWN_PHY_LOWGAINDB BWN_PHY_OFDM(0x24)
402 #define BWN_PHY_VERYLOWGAINDB BWN_PHY_OFDM(0x25)
403 #define BWN_PHY_GAINMISMATCH BWN_PHY_OFDM(0x26)
404 #define BWN_PHY_ADIVRELATED BWN_PHY_OFDM(0x27)
405 #define BWN_PHY_GAINDIRECTMISMATCH BWN_PHY_OFDM(0x27) /* for LP */
406 #define BWN_PHY_CRS0 BWN_PHY_OFDM(0x29)
408 #define BWN_PHY_PWR_THRESH1 BWN_PHY_OFDM(0x29) /* for LP */
409 #define BWN_PHY_ANTDWELL BWN_PHY_OFDM(0x2b)
411 #define BWN_PHY_DSSS_CONFIRM_CNT BWN_PHY_OFDM(0x2f) /* DSSS Confirm Cnt */
412 #define BWN_PHY_PEAK_COUNT BWN_PHY_OFDM(0x30)
413 #define BWN_PHY_GAIN_MISMATCH_LIMIT BWN_PHY_OFDM(0x31)
414 #define BWN_PHY_CRS_ED_THRESH BWN_PHY_OFDM(0x32)
415 #define BWN_PHY_INPUT_PWRDB BWN_PHY_OFDM(0x34)
416 #define BWN_PHY_AFE_ADC_CTL_0 BWN_PHY_OFDM(0x36)
417 #define BWN_PHY_AFE_ADC_CTL_1 BWN_PHY_OFDM(0x37)
418 #define BWN_PHY_AFE_DAC_CTL BWN_PHY_OFDM(0x39)
419 #define BWN_PHY_AFE_CTL BWN_PHY_OFDM(0x3a)
420 #define BWN_PHY_AFE_CTL_OVR BWN_PHY_OFDM(0x3b)
421 #define BWN_PHY_AFE_CTL_OVRVAL BWN_PHY_OFDM(0x3c)
422 #define BWN_PHY_AFE_RSSI_CTL_0 BWN_PHY_OFDM(0x3d)
423 #define BWN_PHY_AFE_RSSI_CTL_1 BWN_PHY_OFDM(0x3e)
424 #define BWN_PHY_LP_PHY_CTL BWN_PHY_OFDM(0x48)
425 #define BWN_PHY_ENCORE BWN_PHY_OFDM(0x49)
427 #define BWN_PHY_RESET_CTL BWN_PHY_OFDM(0x4a)
428 #define BWN_PHY_RF_OVERRIDE_0 BWN_PHY_OFDM(0x4c)
429 #define BWN_PHY_RF_OVERRIDE_VAL_0 BWN_PHY_OFDM(0x4d)
430 #define BWN_PHY_TR_LOOKUP_1 BWN_PHY_OFDM(0x4e)
431 #define BWN_PHY_TR_LOOKUP_2 BWN_PHY_OFDM(0x4F)
432 #define BWN_PHY_LMS BWN_PHY_OFDM(0x55)
433 #define BWN_PHY_TABLE_ADDR BWN_PHY_OFDM(0x55) /* for LP */
434 #define BWN_PHY_TABLEDATALO BWN_PHY_OFDM(0x56)
435 #define BWN_PHY_TABLEDATAHI BWN_PHY_OFDM(0x57)
436 #define BWN_PHY_OFDM61 BWN_PHY_OFDM(0x61)
438 #define BWN_PHY_ADC_COMPENSATION_CTL BWN_PHY_OFDM(0x70)
439 #define BWN_PHY_OTABLECTL BWN_PHY_OFDM(0x72)
441 #define BWN_PHY_OTABLEI BWN_PHY_OFDM(0x73)
442 #define BWN_PHY_OTABLEQ BWN_PHY_OFDM(0x74)
443 #define BWN_PHY_HPWR_TSSICTL BWN_PHY_OFDM(0x78)
444 #define BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR BWN_PHY_OFDM(0x81)
445 #define BWN_PHY_IQ_NUM_SMPLS_ADDR BWN_PHY_OFDM(0x82)
446 #define BWN_PHY_IQ_ACC_HI_ADDR BWN_PHY_OFDM(0x83)
447 #define BWN_PHY_IQ_ACC_LO_ADDR BWN_PHY_OFDM(0x84)
448 #define BWN_PHY_IQ_I_PWR_ACC_HI_ADDR BWN_PHY_OFDM(0x85)
449 #define BWN_PHY_IQ_I_PWR_ACC_LO_ADDR BWN_PHY_OFDM(0x86)
450 #define BWN_PHY_IQ_Q_PWR_ACC_HI_ADDR BWN_PHY_OFDM(0x87)
451 #define BWN_PHY_IQ_Q_PWR_ACC_LO_ADDR BWN_PHY_OFDM(0x88)
452 #define BWN_PHY_ANTWRSETT BWN_PHY_OFDM(0x8c)
454 #define BWN_PHY_OFDM9B BWN_PHY_OFDM(0x9b)
455 #define BWN_PHY_A_PHY_CTL_ADDR BWN_PHY_OFDM(0x9c)
456 #define BWN_PHY_RX_COMP_COEFF_S BWN_PHY_OFDM(0x9e)
457 #define BWN_PHY_N1P1GAIN BWN_PHY_OFDM(0xa0)
458 #define BWN_PHY_SMPL_PLAY_COUNT BWN_PHY_OFDM(0xa0) /* for LP */
459 #define BWN_PHY_P1P2GAIN BWN_PHY_OFDM(0xa1)
460 #define BWN_PHY_SMPL_PLAY_BUFFER_CTL BWN_PHY_OFDM(0xA1) /* for LP */
461 #define BWN_PHY_N1N2GAIN BWN_PHY_OFDM(0xa2)
462 #define BWN_PHY_4WIRECTL BWN_PHY_OFDM(0xa2) /* for LP */
463 #define BWN_PHY_TX_PWR_CTL_CMD BWN_PHY_OFDM(0xa4)
468 #define BWN_PHY_CCKSHIFTBITS_WA BWN_PHY_OFDM(0xa5)
469 #define BWN_PHY_TX_PWR_CTL_NNUM BWN_PHY_OFDM(0xa5) /* for LP */
470 #define BWN_PHY_CCKSHIFTBITS BWN_PHY_OFDM(0xa7)
471 #define BWN_PHY_DIVSRCHIDX BWN_PHY_OFDM(0xa8)
472 #define BWN_PHY_DIVP1P2GAIN BWN_PHY_OFDM(0xab)
473 #define BWN_PHY_LP_RF_SIGNAL_LUT BWN_PHY_OFDM(0xac)
474 #define BWN_PHY_DIVSRCHGAINBACK BWN_PHY_OFDM(0xad)
475 #define BWN_PHY_RX_RADIO_CTL BWN_PHY_OFDM(0xae)
476 #define BWN_PHY_RF_OVERRIDE_2 BWN_PHY_OFDM(0xb0)
477 #define BWN_PHY_RF_OVERRIDE_2_VAL BWN_PHY_OFDM(0xb1)
478 #define BWN_PHY_PS_CTL_OVERRIDE_VAL0 BWN_PHY_OFDM(0xB2)
479 #define BWN_PHY_PS_CTL_OVERRIDE_VAL1 BWN_PHY_OFDM(0xB3)
480 #define BWN_PHY_PS_CTL_OVERRIDE_VAL2 BWN_PHY_OFDM(0xB4)
481 #define BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL BWN_PHY_OFDM(0xB5)
482 #define BWN_PHY_RX_GAIN_CTL_OVERRIDE_VAL BWN_PHY_OFDM(0xB6)
483 #define BWN_PHY_AFE_DDFS BWN_PHY_OFDM(0xb7)
484 #define BWN_PHY_AFE_DDFS_POINTER_INIT BWN_PHY_OFDM(0xB8)
485 #define BWN_PHY_AFE_DDFS_INCR_INIT BWN_PHY_OFDM(0xB9)
486 #define BWN_PHY_TR_LOOKUP_3 BWN_PHY_OFDM(0xbb)
487 #define BWN_PHY_TR_LOOKUP_4 BWN_PHY_OFDM(0xbc)
488 #define BWN_PHY_GPIO_OUTEN BWN_PHY_OFDM(0xbe)
489 #define BWN_PHY_GPIO_SELECT BWN_PHY_OFDM(0xbf)
490 #define BWN_PHY_CRSTHRES1 BWN_PHY_OFDM(0xc0)
491 #define BWN_PHY_CRSTHRES2 BWN_PHY_OFDM(0xc1)
492 #define BWN_PHY_4C3 BWN_PHY_OFDM(0xC3)
493 #define BWN_PHY_4C4 BWN_PHY_OFDM(0xC4)
494 #define BWN_PHY_4C5 BWN_PHY_OFDM(0xC5)
495 #define BWN_PHY_TR_LOOKUP_5 BWN_PHY_OFDM(0xC7)
496 #define BWN_PHY_TR_LOOKUP_6 BWN_PHY_OFDM(0xC8)
497 #define BWN_PHY_TR_LOOKUP_7 BWN_PHY_OFDM(0xC9)
498 #define BWN_PHY_TR_LOOKUP_8 BWN_PHY_OFDM(0xCA)
499 #define BWN_PHY_RF_PWR_OVERRIDE BWN_PHY_OFDM(0xd3)