Lines Matching refs:tim
2925 uint64_t tim : 1; /**< TIM interrupt-enable */
2949 uint64_t tim : 1;
2981 uint64_t tim : 1; /**< TIM interrupt-enable */
3005 uint64_t tim : 1;
3044 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
3068 uint64_t tim : 1;
3100 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
3124 uint64_t tim : 1;
3163 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
3187 uint64_t tim : 1;
3219 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
3243 uint64_t tim : 1;
4029 uint64_t tim : 1; /**< TIM interrupt-enable */
4053 uint64_t tim : 1;
4085 uint64_t tim : 1; /**< TIM interrupt-enable */
4109 uint64_t tim : 1;
4148 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
4172 uint64_t tim : 1;
4204 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
4228 uint64_t tim : 1;
4267 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
4291 uint64_t tim : 1;
4323 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
4347 uint64_t tim : 1;
5133 uint64_t tim : 1; /**< TIM interrupt-enable */
5157 uint64_t tim : 1;
5189 uint64_t tim : 1; /**< TIM interrupt-enable */
5213 uint64_t tim : 1;
5252 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
5276 uint64_t tim : 1;
5308 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
5332 uint64_t tim : 1;
5371 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
5395 uint64_t tim : 1;
5427 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
5451 uint64_t tim : 1;
6237 uint64_t tim : 1; /**< TIM interrupt-enable */
6261 uint64_t tim : 1;
6293 uint64_t tim : 1; /**< TIM interrupt-enable */
6317 uint64_t tim : 1;
6356 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
6380 uint64_t tim : 1;
6412 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
6436 uint64_t tim : 1;
6475 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
6499 uint64_t tim : 1;
6531 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
6555 uint64_t tim : 1;
7217 uint64_t tim : 1; /**< TIM interrupt
7250 uint64_t tim : 1;
7289 uint64_t tim : 1; /**< TIM interrupt
7322 uint64_t tim : 1;
7642 uint64_t tim : 1; /**< TIM interrupt
7675 uint64_t tim : 1;
7714 uint64_t tim : 1; /**< TIM interrupt
7747 uint64_t tim : 1;
8067 uint64_t tim : 1; /**< TIM interrupt
8100 uint64_t tim : 1;
8139 uint64_t tim : 1; /**< TIM interrupt
8172 uint64_t tim : 1;
8492 uint64_t tim : 1; /**< TIM interrupt
8525 uint64_t tim : 1;
8564 uint64_t tim : 1; /**< TIM interrupt
8597 uint64_t tim : 1;
8936 uint64_t tim : 1; /**< TIM interrupt source
8968 uint64_t tim : 1;
9007 uint64_t tim : 1; /**< TIM interrupt source
9039 uint64_t tim : 1;
9376 uint64_t tim : 1; /**< TIM interrupt source
9408 uint64_t tim : 1;
9447 uint64_t tim : 1; /**< TIM interrupt source
9479 uint64_t tim : 1;
9819 uint64_t tim : 1; /**< TIM interrupt source
9851 uint64_t tim : 1;
9890 uint64_t tim : 1; /**< TIM interrupt source
9922 uint64_t tim : 1;
10259 uint64_t tim : 1; /**< TIM interrupt source
10291 uint64_t tim : 1;
10330 uint64_t tim : 1; /**< TIM interrupt source
10362 uint64_t tim : 1;