utils/TableGen/CodeGenSchedule.cpp

190     RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
298     findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence,
388                                  IdxVec &Writes, IdxVec &Reads) const {
392     findRWs(WriteDefs, Writes, false);
515     IdxVec Writes, Reads;
517       findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
522     unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices);
558     if (!SC.Writes.empty()) {
561       for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes.end(); WI != WE; ++WI)
574       IdxVec Writes;
577               Writes, Reads);
578       for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI)
596                                                const IdxVec &Writes,
600         && I->Writes == Writes && I->Reads == Reads) {
669   SC.Writes = OperWrites;
723     // Preserve ItinDef and Writes/Reads for processors without an InstRW entry.
725     SC.Writes = SchedClasses[OldSCIdx].Writes;
838     if (!SchedClasses[Idx].Writes.empty()) {
839       inferFromRW(SchedClasses[Idx].Writes, SchedClasses[Idx].Reads,
864       IdxVec Writes, Reads;
865       findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
867       inferFromRW(Writes, Reads, FromClassIdx, ProcIndices);
886     IdxVec Writes, Reads;
887     findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
890     inferFromRW(Writes, Reads, SCIdx, ProcIndices);
1123 // Push the Reads/Writes selected by this variant onto the PredTransition
1190 // RWSeq is a sequence of all Reads or all Writes for the next read or write
1230 // Read/Writes guarded by the variant. This is exponential in the number of
1231 // variant Read/Writes, but in practice detection of mutually exclusive
1437           IdxVec Writes, Reads;
1439                   Writes, Reads);
1440           collectRWResources(Writes, Reads, ProcIndices);
1443       collectRWResources(SCI->Writes, SCI->Reads, SCI->ProcIndices);
1510       IdxVec Writes, Reads;
1511       findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
1513       collectRWResources(Writes, Reads, ProcIndices);
1557 void CodeGenSchedModels::collectRWResources(const IdxVec &Writes,
1561   for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI)
1693          << "  Writes: ";
1694   for (unsigned i = 0, N = Writes.size(); i < N; ++i) {
1695     SchedModels->getSchedWrite(Writes[i]).dump();