Lines Matching refs:IsRead
285 assert(!getSchedRWIdx(*SWI, /*IsRead=*/false) && "duplicate SchedWrite");
290 assert(!getSchedRWIdx(*SRI, /*IsRead-*/true) && "duplicate SchedWrite");
299 /*IsRead=*/false);
334 std::string CodeGenSchedModels::genRWName(const IdxVec& Seq, bool IsRead) {
339 Name += getSchedRW(*I, IsRead).Name;
345 unsigned CodeGenSchedModels::getSchedRWIdx(Record *Def, bool IsRead,
347 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
398 bool IsRead) const {
400 unsigned Idx = getSchedRWIdx(*RI, IsRead);
407 bool IsRead) const {
408 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead);
418 expandRWSequence(*I, RWSeq, IsRead);
426 unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
429 const CodeGenSchedRW &SchedWrite = getSchedRW(RWIdx, IsRead);
446 expandRWSeqForProc(getSchedRWIdx(AliasDef, IsRead),
447 RWSeq, IsRead,ProcModel);
459 expandRWSeqForProc(*I, RWSeq, IsRead, ProcModel);
466 bool IsRead) {
467 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
480 bool IsRead) {
485 unsigned Idx = findRWForSequence(Seq, IsRead);
489 unsigned RWIdx = IsRead ? SchedReads.size() : SchedWrites.size();
490 CodeGenSchedRW SchedRW(RWIdx, IsRead, Seq, genRWName(Seq, IsRead));
491 if (IsRead)
909 bool IsRead;
913 PredCheck(bool r, unsigned w, Record *p): IsRead(r), RWIdx(w), Predicate(p) {}
936 bool IsRead, unsigned StartIdx);
949 void pushVariant(const TransVariant &VInfo, bool IsRead);
970 const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(I->RWIdx, I->IsRead);
993 SchedModels.expandRWSequence(AliasRW.Index, ExpandedRWs, AliasRW.IsRead);
996 if (hasAliasedVariants(SchedModels.getSchedRW(*SI, AliasRW.IsRead),
1126 pushVariant(const TransVariant &VInfo, bool IsRead) {
1138 Trans.PredTerm.push_back(PredCheck(IsRead, VInfo.RWIdx,PredDef));
1140 SchedModels.findRWs(SelectedDefs, SelectedRWs, IsRead);
1145 SelectedRWs.push_back(SchedModels.getSchedRWIdx(VInfo.VarOrSeqDef, IsRead));
1148 const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(VInfo.RWIdx, IsRead);
1150 SmallVectorImpl<SmallVector<unsigned,4> > &RWSequences = IsRead
1165 if (IsRead)
1168 SchedModels.expandRWSequence(*RWI, ExpandedRWs, IsRead);
1181 if (IsRead)
1184 SchedModels.expandRWSequence(*RWI, ExpandedRWs, IsRead);
1195 const SmallVectorImpl<unsigned> &RWSeq, bool IsRead, unsigned StartIdx) {
1200 const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(*RWI, IsRead);
1208 if (IsRead)
1223 pushVariant(*IVI, IsRead);
1252 substituteVariantOperand(*WSI, /*IsRead=*/false, StartIdx);
1263 substituteVariantOperand(*RSI, /*IsRead=*/true, StartIdx);
1281 SchedModels.findOrInsertRW(*WSI, /*IsRead=*/false));
1289 SchedModels.findOrInsertRW(*RSI, /*IsRead=*/true));
1328 expandRWSequence(*I, WriteSeq, /*IsRead=*/false);
1339 expandRWSequence(*I, ReadSeq, /*IsRead=*/true);
1518 void CodeGenSchedModels::collectRWResources(unsigned RWIdx, bool IsRead,
1520 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead);
1522 if (!IsRead && SchedRW.TheDef->isSubClassOf("SchedWriteRes")) {
1528 else if (IsRead && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) {
1545 assert(AliasRW.IsRead == IsRead && "cannot alias reads to writes");
1548 expandRWSequence(AliasRW.Index, ExpandedRWs, IsRead);
1551 collectRWResources(*SI, IsRead, AliasProcIndices);
1562 collectRWResources(*WI, /*IsRead=*/false, ProcIndices);
1565 collectRWResources(*RI, /*IsRead=*/true, ProcIndices);
1729 dbgs() << SchedModels.getSchedRW(PCI->RWIdx, PCI->IsRead).Name