Lines Matching defs:LD

95   SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, DebugLoc dl);
96 SDNode *SelectIndexedLoad(LoadSDNode *LD, DebugLoc dl);
97 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
99 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
388 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, DebugLoc dl) {
389 SDValue Chain = LD->getChain();
390 SDNode* Const32 = LD->getBasePtr().getNode();
394 ISD::isNormalLoad(LD)) {
396 EVT LoadedVT = LD->getMemoryVT();
417 LD->getValueType(0),
423 MemOp[0] = LD->getMemOperand();
425 ReplaceUses(LD, Result);
430 return SelectCode(LD);
434 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
438 SDValue Chain = LD->getChain();
439 EVT LoadedVT = LD->getMemoryVT();
440 SDValue Base = LD->getBasePtr();
441 SDValue Offset = LD->getOffset();
444 SDValue N1 = LD->getOperand(1);
457 MemOp[0] = LD->getMemOperand();
459 const SDValue Froms[] = { SDValue(LD, 0),
460 SDValue(LD, 1),
461 SDValue(LD, 2)
481 MemOp[0] = LD->getMemOperand();
483 const SDValue Froms[] = { SDValue(LD, 0),
484 SDValue(LD, 1),
485 SDValue(LD, 2)
494 return SelectCode(LD);
498 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
502 SDValue Chain = LD->getChain();
503 EVT LoadedVT = LD->getMemoryVT();
504 SDValue Base = LD->getBasePtr();
505 SDValue Offset = LD->getOffset();
508 SDValue N1 = LD->getOperand(1);
526 MemOp[0] = LD->getMemOperand();
528 const SDValue Froms[] = { SDValue(LD, 0),
529 SDValue(LD, 1),
530 SDValue(LD, 2)
557 MemOp[0] = LD->getMemOperand();
559 const SDValue Froms[] = { SDValue(LD, 0),
560 SDValue(LD, 1),
561 SDValue(LD, 2)
571 return SelectCode(LD);
575 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, DebugLoc dl) {
576 SDValue Chain = LD->getChain();
577 SDValue Base = LD->getBasePtr();
578 SDValue Offset = LD->getOffset();
582 EVT LoadedVT = LD->getMemoryVT();
586 bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
613 if (LD->getValueType(0) == MVT::i64 &&
614 LD->getExtensionType() == ISD::ZEXTLOAD) {
615 return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
617 if (LD->getValueType(0) == MVT::i64 &&
618 LD->getExtensionType() == ISD::SEXTLOAD) {
620 return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
625 LD->getValueType(0),
629 MemOp[0] = LD->getMemOperand();
631 const SDValue Froms[] = { SDValue(LD, 0),
632 SDValue(LD, 1),
633 SDValue(LD, 2)
645 LD->getValueType(0),
652 MemOp[0] = LD->getMemOperand();
654 const SDValue Froms[] = { SDValue(LD, 0),
655 SDValue(LD, 1),
656 SDValue(LD, 2)
671 LoadSDNode *LD = cast<LoadSDNode>(N);
672 ISD::MemIndexedMode AM = LD->getAddressingMode();
676 result = SelectIndexedLoad(LD, dl);
678 result = SelectBaseOffsetLoad(LD, dl);
850 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
851 if (LD->getMemoryVT() != MVT::i32 ||
852 LD->getExtensionType() != ISD::SEXTLOAD ||
853 LD->getAddressingMode() != ISD::UNINDEXED) {
857 SDValue Chain = LD->getChain();
861 LD->getBasePtr(), TargetConst0,
876 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
877 if (LD->getMemoryVT() != MVT::i32 ||
878 LD->getExtensionType() != ISD::SEXTLOAD ||
879 LD->getAddressingMode() != ISD::UNINDEXED) {
883 SDValue Chain = LD->getChain();
887 LD->getBasePtr(), TargetConst0,
1030 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
1031 if (LD->getMemoryVT() != MVT::i32 ||
1032 LD->getExtensionType() != ISD::SEXTLOAD ||
1033 LD->getAddressingMode() != ISD::UNINDEXED) {
1037 SDValue Chain = LD->getChain();
1041 LD->getBasePtr(),
1055 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
1056 if (LD->getMemoryVT() != MVT::i32 ||
1057 LD->getExtensionType() != ISD::SEXTLOAD ||
1058 LD->getAddressingMode() != ISD::UNINDEXED) {
1062 SDValue Chain = LD->getChain();
1066 LD->getBasePtr(),