CodeGen/SelectionDAG/LegalizeDAG.cpp

263                            (VT == MVT::f64) ? MVT::i64 : MVT::i32);
667       if (TLI.isTypeLegal(MVT::i64)) {
669                                   zextOrTrunc(64), MVT::i64);
1989   case MVT::i64:  LC = Call_I64; break;
2004   case MVT::i64:  LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2051   case MVT::i64:  LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2280   assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2283   // Implementation of unsigned i64 to f64 following the algorithm in
2288   if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2290       DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2294       DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2297     SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2298                              DAG.getConstant(32, MVT::i64));
2299     SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2300     SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2308   // Implementation of unsigned i64 to f32.
2310   if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2318       SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2319       SDValue AndConst = DAG.getConstant(1, MVT::i64);
2320       SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2321       SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2330       SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2331         Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2337     SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2338          DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2339     SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2340          DAG.getConstant(UINT64_C(0x800), MVT::i64));
2341     SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2342          DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2343     SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2344                    And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2345     SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2346     SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2347                    Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2349     SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2352     SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2384   case MVT::i64: FF = 0x5F800000ULL; break;  // 2^64 (as a float)
2517   case MVT::i64:
2652     case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2661     case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2670     case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2679     case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2688     case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2697     case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2706     case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2715     case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
3497       else if (WideVT == MVT::i64)